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Requirements:
* B.Sc. in Computer Science / Electrical Engineering / Computer Engineering.
* At least 3 years of development experience in a development team of complex enterprise systems.
* At least 2 years of experience in C / C ++ programming.
* Experience in multi-threading principles and programming.
* Experience in Python, JAVA, Linux, and Git.
* Great team player who knows when and how to push independently when needed.
* Strong communication skills.
Advantages:
* Experience in native mobile application development in Android or IOS.
* Experience Objective- C programming.
* Experience in NDK and JNI for Android.
* Experience with SDK development or integration. Advantages.
* Experience in reverse engineering for Android.
* Knowledge in Cyber security and Networking.
About the company:
Our mission is to protect every mobile app in the world and its users. We provide mobile brands with the only patented, centralized, data -driven Mobile Cyber Defense Automation platform. Our platform delivers rapid no-code, no-SDK mobile app security, anti-fraud, anti-malware, anti-cheat, anti-bot implementations, configuration as code ease, Threat-Events threat-aware UI / UX control, ThreatScope Mobile XDR, and Certified Secure DevSecOps Certification in one integrated system. With us, mobile Developers, cyber and fraud teams can accelerate delivery, guarantee compliance, and leverage automation to build, TEST, release, and monitor the full range of cyber, anti-fraud, and other defenses needed in mobile apps from within mobile DevOps and CI/CD pipelines. Leading financial, healthcare, m-commerce, consumer, and B2B brands use us to upgrade mobile DevSecOps and protect Android & IOS apps, mobile customers, and businesses globally. Today, our customers use our platform to secure over 50,000+ mobile apps, with protection for over 1 billion mobile end users projected.
We are an Equal Opportunity Employer. We are committed to diversity, equity, and inclusion in our workplace. We do not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other characteristic protected by law. All qualified applicants will receive consideration for employment without regard to any of these characteristics.

Requirements:
An ideal candidate will have at least 10 years of work experience in RTL design, SoC integration, memory controller and interconnect IP design.

Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Minimum Skills and Experience:

Experience with memory sub systems and bus architecture.

Required Skills and Experience :

BS/MS in Electrical and/or Computer Engineering with over 10 years of experience.

Knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI) is a plus.

Experience with Verilog, coupled with design synthesis targeted to achieve specified frequency, power, and area targets.

Processor system knowledge includes basic understanding of SoC systems as well as operating system software is a plus.

Great communication & teamwork skills.

Requirements:
B.S. degree in a hard science, engineering, computer science, or a related field; advanced degrees are a plus (M.Sc. or Ph.D.).
Hands-on experience with development in one or more HPC application domains.
Proficiency in C/C++ and/or Fortran.
Ability to measure application-level performance and profile HPC applications at the node level and at scale.
Working understanding of OpenMP, MPI, and related parallel programming models.
Expertise in competitive performance analysis is strongly preferred.
Ability to work remotely and independently in a fast-paced environment, with minimal supervision.
Knowledge of low-level CPU and/or GPU architecturean advantage.

Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years experience in STA (Prime-Time/Signoff).
Experience Full chip STA on complex SoCs experience.
Expert knowledge and hands-on experience in timing closure & signoff methodologies.
Good knowledge of DFT architecture and DFT timing related issues
Good knowledge of Async timing concepts & verification.
Good knowledge of the full backend flows from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs)