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As a Software Engineer - Modi'in, you will take part in building scalable, high-performance systems that power some of the largest digital marketing platforms in the world. You will be responsible for developing end-to-end features while working with cutting-edge technologies and handling real-world scale. You will collaborate closely with Product Managers, UX designers, architects, engineers, and cross-functional teams to shape product direction and deliver high-quality solutions. As part of a strong, experienced team, you will contribute to architectural decisions, and continuously push the boundaries of what our platform can do.

Key Responsibilities

Design, implement, and deploy end-to-end features and products, spanning from database and backend services to client-facing components.
Tackle complex, large-scale technical challenges, ensuring the performance, scalability, and reliability of platform and infrastructure.
Collaborate with Product Managers, UX designers, architects, and cross-functional teams to deliver high-quality, impactful solutions while shaping product direction.
Analyze and optimize the performance, scalability, and reliability of our products, infrastructure, and internal tools.
Work with GenAi coding assistants
Proactively research and implement emerging technologies to continuously enhance our platform offerings.

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.
Taking part in flows development and deployment.