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our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Layout activities for complex Sub Full Chip with several levels of hierarchies.
Floorplanning, top-down deliveries & bottom up rollup , Sub FC/ IP level integration & verification.
Signoff on all physical design domains PV, IR/EM, LEC, LP Verification.
Physical Verification expert, building, maintaining and enhancing the flow for new technologies, improving reliability & convergence ToT.
Servings as a technical expert while mentoring and guiding team members,
Hands-on physical design block owner from RTL to GDS , an option.

Developing UI for operational systems featuring maps and a geographic situational picture
Leading technical aspects of the Frontend domain
Migrating an existing system to a modern Web environment

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

we are at the forefront of developing autonomous driving systems. our company state-of-the-art ECUs are integrated into vehicles from leading OEMs and enable its leading autonomous driving solutions. Are you passionate about designing cutting-edge solutions for complex, high-impact challenges? Do you have an eye for detail and a knack for seeing the bigger picture? At our company, our Platform Architecture team plays a pivotal role in seamlessly shaping system architecture into high-performance systems that drive the future of autonomous driving. By joining us, youll collaborate with top engineers to develop innovative systems that not only shape the evolution of our industry-leading products, but also contribute to advancing the future of mobility. As part of our mission, youll play a key role in making the world a safer place through autonomous driving technology.
What will your job look like?
Define System Architecture: Develop system requirements and architecture that align with customer needs and our company's software and hardware products.
Design and define: system architectures and flows for critical functions, including boot processes, power-on sequences, system health monitoring, and diagnostics, ensuring robust and reliable platform performance.
Engage with customers: analyze and understand customer requirements and maximize alignment with existing solutions.
Collaborate with Product Managers: Ensure requirements are in sync with system architecture and that both software and hardware developments meet system-level objectives.
Work closely with Project Managers: Define, map dependencies, and prioritize the scope of customer releases.
Innovate with Sensing, Driving and Fusion teams: to optimize overall system performance.

we are at the forefront of developing autonomous driving systems. our company state-of-the-art ECUs are integrated into vehicles from leading OEMs and enable its leading autonomous driving solutions. Are you passionate about designing cutting-edge solutions for complex, high-impact challenges? Do you have an eye for detail and a knack for seeing the bigger picture? At our company, our Platform Architecture team plays a pivotal role in seamlessly shaping system architecture into high-performance systems that drive the future of autonomous driving. By joining us, youll collaborate with top engineers to develop innovative systems that not only shape the evolution of our industry-leading products, but also contribute to advancing the future of mobility. As part of our mission, youll play a key role in making the world a safer place through autonomous driving technology.
What will your job look like?
Define System Architecture: Develop system requirements and architecture that align with customer needs and our company's software and hardware products.
Design and define: system architectures and flows for critical functions, including boot processes, power-on sequences, system health monitoring, and diagnostics, ensuring robust and reliable platform performance.
Engage with customers: analyze and understand customer requirements and maximize alignment with existing solutions.
Collaborate with Product Managers: Ensure requirements are in sync with system architecture and that both software and hardware developments meet system-level objectives.
Work closely with Project Managers: Define, map dependencies, and prioritize the scope of customer releases.
Innovate with Sensing, Driving and Fusion teams: to optimize overall system performance.

Geographic Asset Surveyor to join our team and support real estate and asset consulting projects.

Key Responsibilities:

Collecting data and information from various geographic information databases.
Analyzing permit plans, area calculations, and financial data.
Conducting field surveys for geographic data collection.
Producing and regularly updating reports.
No prior experience required full training provided by the company!

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.