Our Analog Layout design team is looking for a Senior Analog Layout Design Engineer someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. We have continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our lifes work, to amplify human creativity and intelligence.
What you'll be doing:
Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools.
You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis.
Requirements: What we need to see:
You will have a minimum of 8 years of relevant mask analog layout experience.
An Electronics Practical Engineer certificate or a B.Sc. in Electrical Engineering.
Proven understanding of analog circuit layout concepts in submicron CMOS technologies - such as Operational Amplifiers and ADC/DACs.
You are an expert with Cadence custom circuit design tools - particularly Virtuoso.
Experience running and debugging DRC and LVS with verification tools such as ICV, Calibre.
You can work effectively in a team, good interpersonal skills, enthusiasm and positive energy.
Ways to stand out in the crowd:
Proficiency in scripting languages like python, skill.
Knowledge of DRC and LVS checking flows, EM/IR tools, ability to customize DRC and LVS decks.
This position is open to all candidates.
