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We are looking for a Senior Application Engineer to join a global team of Application Engineers that own a technical success and customer satisfaction across multiple high-impact projects.
Requirements
Responsibilities
Provide close support to customers and deploy our technology across multiple projects
Provide training to customers on our tools and present our technology
Ability to plan, prioritize tasks/issues and take them to full resolution
Provide continuous feedback to R&D to improve the product.

Were growing and looking for a hands-on CAD Engineer who loves building tools that engineers actually enjoy using.
If you like moving fast, owning features end-to-end, and collaborating with smart people across disciplines-come build with us.
Responsibilities
Partnering with multiple engineering disciplines to define, improve, and maintain CAD/EDA development methodologies
Building CAD desktop applications that support EDA solutions and real design workflows
Writing production-quality code, plus unit tests that keep things solid as we scale
The team's vibe:
We value innovation, teamwork, and ownership
Youll have real impact, real autonomy, and a team that actually ships.

The Signal-Integrity & Packaging (SIP) team manages the external electrical interfaces of Annapurna Lab's chip devices, focusing on signal integrity, power integrity, and electrical usage.
The team collaborates with the BackEnd team to integrate interfaces into the die, designs package layouts for BGA substrates, and conducts signal and power integrity simulations. The team partners with the system team to develop optimal pin-out and PCB breakout schemes, performs electrical characterization of interfaces, and develops software tools for debug and diagnostics.

As a SIP team member, the scope of your work will be focused on Package substrate layout, with a blend of Signal & Power integrity extractions and simulations, as well as also influencing the DIE I/O structures.

Key job responsibilities:
Design and Layout of large and complex package substrates.
Understanding package substrate technologies and layout design rules.
Proficiency in Signal and Power Integrity considerations.
Layout test studies of Die bump-out structures and Package substrate breakout.
Layout test studies of Package pin-out arrangements and PCB board implementation.
Continuously improve the package design work, by coming up with initiatives that drive efficiency, and in turn help improve quality/cost/schedule of the package layout work.

The position is for an entry level, and we will teach and mentor all aspects of the role. No prior hands-on experience in the above list is required.

We are looking for a Senior Machine Learning Algorithm Engineer who is passionate about solving complex, real-world problems at the intersection of hardware and software.
Location: Haifa \ Tel-Aviv in hybrid model.
Responsibilities
Develop advanced ML algorithms using data from our company Agents embedded in silicon. Example domains include:
Lifetime predictions
Clustering and dimensionality reduction
Parametric modeling and screening
Time-series forecasting
Lead end-to-end algorithm lifecycle: ideation → research → POC → design → implementation → validation → deployment.
Collaborate closely with cross-functional teams and directly with customers to continuously refine and enhance deployed solutions.
Drive integration of AI-enhanced tools and intelligent pipelines into ML workflows.

We are looking for a Senior Machine Learning Algorithm Engineer who is passionate about solving complex, real-world problems at the intersection of hardware and software.
Location: Haifa \ Tel-Aviv in hybrid model.
Responsibilities
Develop advanced ML algorithms using data from our company Agents embedded in silicon. Example domains include:
Lifetime predictions
Clustering and dimensionality reduction
Parametric modeling and screening
Time-series forecasting
Lead end-to-end algorithm lifecycle: ideation → research → POC → design → implementation → validation → deployment.
Collaborate closely with cross-functional teams and directly with customers to continuously refine and enhance deployed solutions.
Drive integration of AI-enhanced tools and intelligent pipelines into ML workflows.

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.