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we are looking for a CPU Silicon Validation Lead, Google Cloud
Responsibilities
Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation or FPGA platforms.
Lead the debugging and resolution of silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.

we are looking for a Firmware Engineer, Networking, Google Cloud
Responsibilities
Build C/C++ firmware running on embedded processors with limited memory footprints on the SoCs.
Develop tools to update and debug the firmware, enable emulation, chip bringup, and hardware debugging.
Play key roles in Emulation, chip bring up, and SoC deployment, and contribute to all layers of the data center software stack to deploy SoCs to production.
Create code generators to generate C++ code based on hardware specifications.

As a CPU Workload Analysis Researcher within Google Cloud's MSCA organization, you will be integral to developing silicon solutions powering Google's direct-to-consumer products. You will join a Research and Development team focused on analyzing and profiling workloads requirements within the Google Cloud environment. Your role will involve conducting in-depth research on CPU optimization, feature development, and ML usages over compute platforms, contributing to identifying key areas of investment and future opportunities. This role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. Your work will directly influence the next generation of hardware experiences for millions of Google users and Cloud customers.

Responsibilities
Plan and execute detailed analysis of CPU workloads within the Google Cloud infrastructure, analyze trends and map future requirements.
Collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to CPU performance and efficiency.
Develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on Google Cloud platforms.
Analyze the impact of machine learning applications on CPU usage, identifying opportunities for optimization and feature enhancements.
Lead the investigation and development of metrics to measure CPU performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.

we are looking for a CPU Logic Design Engineer, Google Cloud, PhD, University Graduate, Start 2025
Responsibilities
Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
Deliver designs meeting Power, performance, and area (PPA) goals with production quality.
Become familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.

As a SERDES/PCIe Silicon Validation Engineer, you will take ownership on characterization of SERDES analog IPs provided by external vendors. Your job is to assure that the IP is meeting Google high standards. You will work closely with different multi-functional teams within the Silicon organization, as well as external vendors.

Responsibilities
Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
Write Inhouse tools/scripts to characterize the IP.
Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.

As an Executive CPU Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-randomn test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through rigorous corner-case testing.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASIC) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

You will be responsible for performance analysis for an end-to-end networking stack using your infornation of RDMA based transports.

Responsibilities
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.

We are looking for a highly motivated backend software engineer specializing in creating high-scale, distributed backend systems.
You must demonstrate strong software engineering skills, excellent interpersonal communication, extreme ownership, and the ability to accept and give meaningful technical feedback.
You will be responsible for designing architecture, writing correct, robust code, maintaining and improving existing functionality, and shipping new features.
You will work as part of a Scrum-Agile cross-functional team and collaborate with front-end engineers, quality engineers, product managers, and more.
The platform you help us build will scale novel functionality to millions of Plus users worldwide.
Our team strives to set the bar for real-time, high-scale, mission-critical trading systems. We want to work with people who are excited by this goal and have the talent to deliver on it.
What Youll Do - Responsibilities:
Design and build scalable, high-availability mission-critical systems and APIs
Drive the migration of large-scale, distributed trading services towards cloud-native microservices
Solve problems using distributed, asynchronous messaging
Tackle technical challenges - performance, fault-tolerance, security, and live production issues
Work closely with product, DevOps\SRE, and infrastructure teams - we practice full-cycle development where developers own and operate what they build.
Mentor Jr engineers as a Senior member of the team

In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Implement designs in SystemVerilog.

We are looking for a highly motivated backend software engineer specializing in creating high-scale, distributed backend systems.
You will design and implement ML/AI infrastructure components (model‑serving APIs, inference pipelines, feature stores).
Collaborate closely with data scientists and data engineers to productionize models and automate retraining workflows.
You must demonstrate strong software engineering skills, excellent interpersonal communication, extreme ownership, and the ability to accept and give meaningful technical feedback.
You will be responsible for designing architecture, writing correct, robust code, maintaining and improving existing functionality, and shipping new features.
You will work as part of a Scrum-Agile cross-functional team and collaborate with front-end engineers, quality engineers, product managers, and more.
The platform you help us build will scale novel functionality to millions of Plus users worldwide.
Our team strives to set the bar for real-time, high-scale, mission-critical trading systems. We want to work with people who are excited by this goal and have the talent to deliver on it.
What Youll Do - Responsibilities:
Containerize and deploy ML models at scale.
Build and maintain CI/CD pipelines for automated model training, testing, and deployment.
Work with data engineers to integrate streaming/batch data into feature pipelines
Design and build scalable, high-availability mission-critical systems and APIs
Drive the migration of large-scale, distributed trading services towards cloud-native microservices
Tackle technical challenges - performance, fault-tolerance, security, and live production issues
Work closely with product, DevOps\SRE, and infrastructure teams - we practice full-cycle development where developers own and operate what they build.

In this role, you will join a Peripheral Component Interconnect Express (PCIe) team and take ownership of post-silicon and pre-silicon validation efforts. You will ensure the Internet Protocol (IP) meets Google's standards while collaborating with cross-functional teams and external vendors.

Responsibilities
Lead or co-lead the PCIe sub system post-silicon logic validation process, including planning, methodology development and co-ordinating with emulation, firmware and testing teams.
Participate in both emulation and post-silicon validation phrases by designing, implementing and excuting tests and tools.
Drive the debugging and resolution of complex silicon issues, collaborating with cross-functional teams across design, architecture, software and firmware.
Analyze validation data to identify trends and root causes and to uncover opportunities for enhancing silicon quality, reliability and performance.

we are looking for a CPU Verification Technical Lead, Google Cloud
Responsibilities
Plan the verification strategy, identify the platform to validate reasoning components.
Define the test plan and strategy with stakeholders, including sign-off and exit criteria.
Plan and execute the verification of Internet Protocols (IPs) using dynamic verification and formal verification.

we are looking for a SoC Verification Technical Lead, Google Cloud
Responsibilities
Plan the verification strategy, identify the platform to validate reasoning components.
Define the test plan and strategy with stakeholders, including sign-off and exit criteria.
Plan and execute the verification of Internet Protocols (IPs) using dynamic verification and formal verification.

we are looking for a Senior CPU Architect, Google Cloud
Responsibilities
Lead architectural definition of CPU core designs, facilitate and make final decisions.
Participate in and influence the building of processor performance analysis infrastructure.
Influence the development of architectural models with varying configurations across product categories.
Perform Performance, Power, Area (PPA) trade-off analysis for architecture and microarchitecture features, communicate analysis results in both qualitative and quantitative fashion to support decisions.

In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical issues with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.

Responsibilities
Own Networking Internet Protocols (IP's) Design team including definition, implementation and deployment.
Define IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.