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Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.

The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

We are looking for an experienced Electrical Engineering Technician with at least 15 years of experience to join our Engineering Group within the Operations Division. The candidate will work closely with the engineering, operations, and maintenance teams to ensure that electrical systems at the company's facilities and sites are operating optimally, while maintaining safety standards and energy efficiency.
What will your job look like:
Design, implement, and maintain electrical systems in industrial and organizational facilities.
Troubleshoot electrical systems and maintain electrical equipment in factories and facilities.
Manage electrical projects, including the design of new electrical systems and upgrades.
Work with contractors and external service providers, including project coordination and supervision.
Perform system checks, preventive maintenance, and installations of electrical equipment.
Adhere to safety protocols and ensure compliance with electrical standards and regulations.
Optimize electrical and energy systems in the companys facilities.

We are looking for talented Engineers to join our Virtual Platforms team.
Virtual platforms play a crucial role in accelerating the development process by enabling early Software development, System-Level testing, and architectural exploration without the constraints of physical prototypes.

As a Virtual Platform Engineer, you will:
Develop accurate and efficient simulation models of hardware components.
Create and maintain Virtual Platform environments for software development and system-level validation.
Debug and optimize complex hardware-software interactions.

We are seeking for System Integration Engineer to help define, shape, and integrate solutions for the next generation of our cloud platforms. As System Integration Engineer youll join Annapurnas product system team, which develops advanced technologies used across our data centers, supporting services like Nitro and Graviton.
You will take ownership of end-to-end system interfaces (e.g., PCIe, Ethernet, DDR) throughout the product lifecycle, from concept to post-deployment debugging.

Key job responsibilities:
1. Setting interface design strategies.
2. Ensuring optimal design implementation.
3. Driving complex system debugs involving hardware, firmware, and software components.
4. Providing leadership to raise quality standards.

The Neuron team works to optimize the performance of complex neural net models on our custom-built our hardware. More specifically, the Neuron team is developing a deep learning compiler stack that takes neural network descriptions created in frameworks such as TensorFlow, PyTorch, and MXNET, and converts them into code suitable for execution. As you might expect, the team is comprised of some of the brightest minds in the engineering, research, and product communities, focused on the ambitious goal of creating a toolchain that will provide a quantum leap in performance.

We are seeking for System Integration Engineer to help define, shape, and integrate solutions for the next generation of our cloud platforms. As System Integration Engineer youll join Annapurnas product system team, which develops advanced technologies used across AWS data centers, supporting services like Nitro and Graviton. You will take ownership of end-to-end system interfaces (e.g., PCIe, Ethernet, DDR) throughout the product lifecycle, from concept to post-deployment debugging.

Key job responsibilities:
1. Setting interface design strategies.
2. Ensuring optimal design implementation.
3. Driving complex system debugs involving hardware, firmware, and software components.
4. Providing leadership to raise quality standards.

As Chief Engineer, you will be responsible for ensuring that all electrical, mechanical, and fire/life safety equipment within the data center is operating at peak efficiency. This involves planned preventative maintenance of equipment, daily corrective work, and emergency response. You are expected to be a singular focal point for all facility operations and to support Amazon within its owned and operated data centers.

You should be able to manage large scale impacting projects and new region support from conception to completion. These projects involve large amounts of independent work as well as collaboration with external support groups including engineering, automation, procurement, and finance in both local and global settings. As Chief Engineer, you will be tasked with creating and delivering on key milestones, obtaining and tracking quotes for all necessary costs, and documenting project results for future implementation at other facilities. The goals of such projects are for the Chief Engineers to drive innovation and resiliency while reducing operational costs in the facilities.

Key job responsibilities
Train and support the Engineering team in their role of providing electrical and mechanical equipment troubleshooting and operations
Implement and execute site or equipment-specific training exercises. Exercises cover, but are not limited to: stand-by diesel generators, switchgear, UPSs, PDUs, AHUs, chillers etc.
Oversee day-to-day operation and maintenance of mechanical and electrical equipment in data center sites
Operate independently, with limited direct management
Assist in the design and build-out of new facilities and perform root cause analysis of equipment failures
Act as an escalation point for all facilities-related issues within the data center region. Work OT hours as needed to support site stability
Troubleshoot and report facility and data sever-level events within internal Service Level Agreements (SLA)
Create and deploy standard practices for Engineering Operations Technicians, Chief Engineers, and vendor support teams
Ensure all safety procedures are adhered to by vendors, and AWS staff.

Our K2Core SW team is looking for a Lead System Test Engineer to define and execute the system validation strategy for the Nitro K2 card. In this technical leadership role, you will own the system-level test definition, drive cross-functional validation efforts, and ensure the end-to-end quality of our Nitro K2 card components deployed across our data centers.

This is a hands-on technical leadership role that requires expertise in embedded systems, hardware/software integration, and test automation at scale. You will work closely with HW, firmware, software, testing and platform teams across us to ensure test coverage, platform integration reliability, and production readiness.

Key job responsibilities:
Define and execute the system-level test and validation strategy for the Nitro K2 card across hardware, firmware, software and platform layers.
Lead the design and development of automated test frameworks to support scalable validation and continuous integration.
Collaborate with hardware, firmware, software, and platform teams to define validation coverage, interfaces, and testability hooks.
Own root cause analysis and debug strategy for complex, cross-subsystem integration issues originating from the production fleet.
Lead and execute hands-on system testing, and participate in the release decision process for production deployment.
Mentor and guide automation engineers, promoting a culture of system-level testing and continuous quality improvement.

Our RADAR VLSI Team is looking for an Embedded SW Engineer for SystemC Modeling that include Performance and Program view Modeling. You will be part of VLSI emulation team , working on current and next-generation designs for next generation sensors.
The SystemC models are fundamental parts of the VLSI chip infrastructure, they are used during HW architecture definition phase and by SW developers for system shift left.
What will your job look like:
You will work on Critical performance analysis and optimizations on the ASIC micro architecture as multi-NOC , DDR and CPU .
You will work on developing SystemC models that describe the RTL models on High level language and enable true system . level shift left for the embedded SW team.
You will have the opportunity to work on state-of-the-art simulation and profiling tools and adopt them to our needs.
You will work closely with HW architects and SW/Algorithms developers.

Required Senior IC Test Engineer
We are the Production Test team - responsible for the definition, development, and deployment of production test operations for the worlds most advanced SoCs for ADAS and self-driving vehicles.
This is your opportunity to join a team during its initial forming stage and leave your mark as we assume full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
What will your job look like:
Work closely with the design teams from early stages of the design process to review DFX architecture and define test requirements.
Define test methodologies and generate test content for high-speed interfaces of embedded IP blocks (LPDDR4/5, PCIe Gen4/5, D/C/MPHY).
Test program coding, pattern conversion and pre-Si validation (virtual test simulations).
Support Load Board and Probe Card design activities.
Lead post-Si test program debug activities to enable delivery of samples to internal and external customers.
Test program characterization and tuning to enhance test program quality to meet automotive standards.
Support Quality & Reliability team to enable effective and timely qual plan execution.
Lead test deployment activities with tier-one Foundry and OSAT vendors to enable large-scale Wafer-Sort and Final-Test operations.

We are looking for an experienced engineer, to help us develop our cutting-edge semiconductor platform.
Youll have the opportunity to join a top-tier, agile, fast-paced team, and take part in the development of the technology that powers the worlds largest cloud provider.
Our Web Services offers a highly reliable, scalable, low-cost cloud platform that enables hundreds of thousands of businesses in 190 countries around the world.
We are looking for talented people to join the Chip Design team in TLV, working on the Nitro product line.
Take an active, significant part in developing the next generations of products that will enable AWS to be the lead in the Cloud sector.

To apply: please compile your CV and university grades sheet into 1 pdf, without both documents, your application cannot be considered.

Key job responsibilities:
Full ownership of one or more IPs within the product:
- Micro-architecture.
- RTL coding and debug.
- Synthesis and timing closure.
- Sign-off.
Supporting the Verification and Emulation teams:
- Test plan.
- Coverage review.
Ensuring that the chip meets quality and reliability standards
Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

Required Power Integrity \ Signal Integrity Engineer
You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of the company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.

Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.