לוח משרות דרושים חשמל ואלקטרוניקה התמחות, לחיפוש זה נמצאו 13 משרות

The Power Design team is responsible for driving power efficiency throughout the chip design lifecycle, from early architecture and RTL through physical implementation and final signoff.
The team develops and owns the methodologies, tools, and flows used to estimate, analyze, track, and optimize chip power. We work closely with architecture, RTL, verification, and physical design teams to identify power challenges early, understand their root causes, and drive effective solutions while balancing power, performance, and area (PPA).
Our work includes developing power models and estimation capabilities, analyzing power at different stages of the design flow, identifying optimization opportunities, and driving improvements at both the RTL and physical design levels. The team also explores new automation and AI-based methodologies to make power analysis faster, more accurate, and more actionable.
As the chips power center of expertise, the team provides technical guidance, establishes best practices, tracks power targets, and drives power-related activities across the broader chip design organization.
What You Can Expect

Ramp up on chip power estimation methodologies, tools, and power calculators.

Perform power analysis and identify optimization opportunities throughout the chip design lifecycle.

Explore and implement power optimizations at both the RTL and physical design levels.

Develop automation and improve existing power analysis and estimation flows.

Explore the use of AI tools for power analysis, optimization, and design-flow automation.

Analyze power trends and identify high-impact areas for improvement.

Collaborate with RTL, physical design, architecture, and power teams to drive power-related activities.

Gradually become a power focal point within the chip design team, building expertise and ownership of power methodologies, analysis, and optimization.

Required Design Verification - Intern
job requisition id
2604481
Your Team, Your Impact
Join a highly skilled development team, driving the development of our next-generation network switches. Our team is responsible for a wide range of IPs for switching products, from initial definition through architecture, design, and verification.
As an intern, you will learn switch architecture, design and verification development tools and modern methodologies. You will be doing hands-on development tasks and learn to become an experienced engineer. You will learn system verilog, UVM, Python, C++, using AI tools, and how to implement and verify complex features. You will investigate and implement new protocols and features and verify them to tapeout quality. We are looking for excellent students, able to handle complex problems, with excellent people relations and collaboration skills.
What You Can Expect:
Implement new features in design and verification.
Reach high-frequency, high-performance, and low-power targets.
Write a verification test plan using random techniques and coverage analysis.
Develop a complex object-oriented random verification environment using System Verilog/UVM.
Create tests and tune the environment to achieve coverage goals.
Own and debug failures in simulation to root cause problems.
Analysis/closure of code and functional coverage.
Use scripting languages to automate repetitive tasks and improve efficiency.

Required Signal Integrity Intern
job requisition id
2604464
Your Team, Your Impact
The Signal Integrity Engineering Group (SIE) is a one-stop shop for all matters related to signal/power integrity (SI/PI), board design, and package design.
The SIE team tailors a board and package design solution that fits every switch product according to the specific device SI/PI, performance, and cost targets and looks at each solution holistically.
Looking at the holistic solution enables each of the SIE group members a unique opportunity to influence switch devices most profoundly and allows us to supply our customers with the most adequate tailored end-to-end solution
What You Can Expect:
Be a part of developing creative power Integrity solutions for our devices at package and system levels.
Evaluate designs to ensure they meet challenging electrical performance requirements.
Collaborate closely with layout engineers and IP teams to optimize power delivery network (PDN) performance.
Be a part of performing simulations, including new EDA tool evaluations, flow development, and scripting for efficiency improvements.
Be a part of developing creative signal integrity solutions for our high speed device interfaces, develop and prove solution with electromagnetic simulation tool.

We are looking for a talented EE/CS student to join the switching department. As a member of the team, you will be responsible for implementing the future devices of routing, using the most challenging, cutting-edge technology. In this role, you will be working with industry-standard tools on the biggest, most complex ASICs the semiconductor industry has to offer.
job requisition id
2604462.

Required Digital IC Design- Intern
job requisition id
2604489
We are seeking a motivated and detail-oriented student to join our Design-for-Test (DFT) team as an ATPG (Automatic Test Pattern Generation) Engineer.
This role offers hands-on experience in the development and implementation of test methodologies for complex SoC designs, focusing on scan insertion, pattern generation, and fault coverage analysis.
Interact with IP teams/vendors to resolve all technical verification issues.
Work closely with design/DV/validation/SW teams
What You Can Expect:
Assist in scan insertion and ATPG flow setup for digital designs.
Generate and validate test patterns for stuck-at and transition faults.
Analyze fault coverage and identify areas for improvement.
Support silicon bring-up and debug of test-related issues.
Collaborate with design and verification teams to ensure testability requirements are met.
Document methodologies, results, and best practices.

Our CTO Office AI Research Group is looking for a motivated advanced BSc student to join our team as a Data Preprocessing Engineer. You will play a foundational role in building the data infrastructure that powers our AI research - working directly with large-scale, real-world datasets at the intersection of machine learning and semiconductor chip design.
job requisition id
2604499
This is a hands-on, high-impact student position for someone who enjoys getting into the details of messy data and turning it into clean, structured, and model-ready assets.
What You Can Expect:
Collect, clean, normalize, and sanitize large-scale chip design datasets from diverse sources and formats
Build and maintain scripts and pipelines to automate repetitive data extraction and transformation tasks
Parse and process a wide variety of file formats (JSON, CSV, Parquet, logs, and domain-specific EDA formats)
Navigate complex codebases and directory structures to locate, understand, and extract relevant data
Work with structured and semi-structured data using SQL and Python-based tooling
Collaborate with researchers and engineers to understand data requirements and deliver model-ready datasets
Document data sources, transformation logic, and dataset versions in shared repositories.

Required Design Verification- Intern
job requisition id
2604479
Your Team, Your Impact:
Join a highly skilled development team, driving the development of our next-generation network switches. Our team is responsible for a wide range of IPs for switching products, from initial definition through architecture, design, and verification.
As an intern, you will learn switch architecture, design and verification development tools and modern methodologies. You will be doing hands-on development tasks and learn to become an experienced engineer. You will learn system verilog, UVM, Python, C++, using AI tools, and how to implement and verify complex features. You will investigate and implement new protocols and features and verify them to tapeout quality. We are looking for excellent students, able to handle complex problems, with excellent people relations and collaboration skills.
What You Can Expect:
Implement new design and verification features.
Reach high-frequency, high-performance, and low-power targets.
Write a verification test plan using random techniques and coverage analysis.
Develop a complex object-oriented random verification environment using System Verilog/UVM.
Create tests and tune the environment to achieve coverage goals.
Own and debug failures in simulation to root-cause problems.
Analysis/closure of code and functional coverage.
Use scripting languages to automate repetitive tasks and improve efficiency.