לוח משרות דרושים מהנדס וריפיקציה | ולידציה משרה מלאה

We are looking for an excellent Verification and Validation System Product Engineer! Our Networking Division is a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. Our products optimize data Center performance and deliver industry-leading bandwidth and scalability. In addition, we serve a wide range of markets including high performance computing, enterprise, data centers, cloud computing, big data, and Web 2.0. We are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry.

What you'll be doing:

Define test strategy.

Design, implement, and execute validation plans for the infrastructure system.

Write efficient, maintainable, and high-quality unit tests for new features and existing codebases

Automate infrastructure testing processes to improve validation efficiency.

Identify potential bottlenecks, vulnerabilities, and failure points within the infrastructure and recommend corrective actions.

Enhance validation efficiency through continuous monitoring and optimization.

Troubleshooting and streamline/optimize our testing procedures.

We are looking for a Formal Verification Engineer for our Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.

Learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.

Our Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like?
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

Our EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

As formal Verification Engineer you'll own verification tasks from planning through execution, collaborating with experienced engineers across multiple teams to ensure design quality while meeting challenging timelines of the Graviton product line. This is an excellent opportunity for motivated engineers to grow their formal verification expertise in a supportive, high-impact environment.

What We Offer:
Mentorship from formal verification experts.
Hands-on experience with cutting-edge cloud compute.
Clear career growth path within us.
Opportunity to impact products used by millions globally.

Key job responsibilities:
- Plan and execute formal verification plans under guidance from senior engineers.
- Develop formal test-benches for design modules.
- Debug formal verification failures and analyze root causes.
- Collaborate with design and verification teams to resolve issues.
- Learn and apply new formal verification methodologies and tools.

Our DDR SoC team is looking for an experienced verification engineer to be involved in the development of our current and future SoC.
Working on the cutting-edge technologies to deliver our EyeQ SoC family for ADAS and autonomous vehicles.
What will your job look like:
Verify the SoC DDR interface including the integration of advanced DDR controller and PHY.
Build block level Verification of the DDR interface
VIP integration for interface protocols and DDR.
Collaborate with designers, architects and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Write and debug tests that combine UVM methodology and SW code.
Define, develop, and execute complex verification scenarios on the DDR interface.

Required Senior Formal Verification Engineer
The Radar VLSI team is looking for an experienced Formal Verification Engineer to join us! This is a newly established team with a mission to integrate Formal Verification as a key methodology in Radar projects. Be part of a cutting-edge group designing chips for radar systems in ADAS and autonomous vehicles, where your expertise will have a significant impact.
What will your job look like:
You will verify unique and complex design blocks.
Help determine the Formal strategy and methodology for the team.
Explore new Formal methods and tools.

We are looking for a System Validation Engineer.
Responsibilities:
System validation activity includes Phy, HW and SW validation.
Study system architecture and system requirements and take part in a test plan to address these requirements in collaboration with system engineering and other teams.
Define and write automatic test plans and test procedures for new systems and features.
Build test setups for fully automated regression as well as for manual tests.
Take active part, hands-on in team execution: integration and feature/product enabling, bring up and debug activities, regression automation test of satellite systems.
Record, investigate and analyze defects.
Investigation of root cause of test case failures and providing corrective action in conjunction with development teams.
Support Test Management tools and continuous integration methodologies.
Data analysis and post processing of data collected.
Compilation of regular Test execution summary report with metrics.

The Radar VLSI team at EyeC is looking for an experienced Formal Verification Engineer to join us! This is a newly established team with a mission to integrate Formal Verification as a key methodology in Radar projects. Be part of a cutting-edge group designing chips for radar systems in ADAS and autonomous vehicles, where your expertise will have a significant impact.
What will your job look like:
You will verify unique and complex design blocks.
Help determine the Formal strategy and methodology for the team.
Explore new Formal methods and tools.

Required Experienced SoC Verification Engineer
Which team will you join?
EyeC VLSI team - a group designing the chips for Radar systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
You will take a central hands-on role in Design Verification.
Define Environment micro-Architect, Implement complex UVM environment, Build vPlan .
Execute coverage implementation.
Be part of external IP verification and Internal custom IP.
Be part of System definition and top-level activity.
Take part in Silicon bring-up.

Required SoC Verification Technical Lead
Which department will you join?
The SOC verification group owns the important and challenging job of verifying our chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

We are seeking for System Validation Engineer to help define, shape, and integrate solutions for the next generation of our cloud platforms.

As a System Validation Engineer at Annapurna Labs, you'll be at the forefront of developing advanced technologies that power the world's largest cloud platform. Your expertise will be critical in ensuring the reliability, performance, and quality of next-generation cloud solutions that support hundreds of thousands of businesses globally.

Key job responsibilities:
- Design, implement, and execute comprehensive test plans and test cases.
- Develop and maintain sophisticated automated test frameworks.
- Identify, document, and track software and system defects with precision.
- Continuously review and enhance quality assurance processes.
- Collaborate closely with development teams to ensure exceptional product quality.

We are looking for a System Validation Engineer Satellite Ground Station .
The LS includes Control and data processing HW, SW as well as Phy and Radio HW and FW, to construct a full communication system supporting DVB-S2X as well as other Radio and IP communication protocols.
 Responsibilities:
Landing station system validation activity including Phy, HW and SW validation.
Study system architecture and system requirements and take part in a test plan to address these requirements in collaboration with system engineering and other teams.
Define and write automatic test plans and test procedures for new systems and features.
Build test setups for fully automated regression as well as for manual tests.
Take active part, hands-on in team execution: integration and feature/product enabling, bring up and debug activities, regression automation test of satellite systems.
Record, investigate and analyze defects.
  Investigation of root cause of test case failures and providing corrective action in conjunction with development teams.
Support Test Management tools and continuous integration methodologies.
  Data analysis and post processing of data collected.
  Compilation of regular Test execution summary report with metrics.

As a Formal Verification Engineer, you'll play a crucial role in ensuring the quality and reliability of our Graviton product line. You'll own the complete verification lifecycle, from planning through execution, collaborating with cross-functional teams to deliver quality results in a fast-paced environment.

Key job responsibilities:
Drive formal verification efforts for complex hardware designs.
Develop comprehensive verification plans and execute them independently.
Collaborate with design, system and verification teams.
Identify and resolve design issues using formal methods.
Contribute to methodology improvements and best practices.

We are looking for a Senior System Validation Engineer.
Responsibilities:
System validation activity including Phy, HW and SW validation.
Study system architecture and system requirements and take part in a test plan to address these requirements in collaboration with system engineering and other teams.
Define and write automatic test plans and test procedures for new systems and features.
Build test setups for fully automated regression as well as for manual tests.
Take active part, hands-on in team execution: integration and feature/product enabling, bring up and debug activities, regression automation test of satellite systems.
Record, investigate and analyze defects.
Investigation of root cause of test case failures and providing corrective action in conjunction with development teams.
Support Test Management tools and continuous integration methodologies.
Data analysis and post processing of data collected.
Compilation of regular Test execution summary report with metrics.