Were looking for a talented Physical Design Engineer to join our VLSI team.
Responsibilities
Manage companys Physical Design field. Including work with remote contractors.
Responsible for full ASIC back-end flow from RTL to GDS for highly complex Mixed signal (digital+analog+RF) SoCs.
In charge of all design flow cycles including: synthesis, STA, LEC, block level PnR, floor-planning, clock and power distribution, power and noise analysis (EM / IR-Drop / Xtalk) as well as knowledge in layout verification (DRC / LVS).
Requirements:
B.Sc. in Electrical Engineering (Electronics).
6+ years of experience as ASIC Back-end engineer.
Experience in advanced CMOS process nodes (double patterning).
Experience in integration of Soft and hard IPs.
Extensive experience with one of the place & route tools available today (Synopsys / Cadence).
Experience with hierarchical design approach, top-down design, timing and physical convergence.
In-depth understanding of static-timing analysis.
Extensive know-how in clock/power distribution and analysis, RC extraction and correlation.
Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Scripting and programming experience using several of the following: Perl, TCL and Python.
Experience with working in Unix environment and version control tools.
Willing to work in dynamic and demanding environment
Fast learner.
A team player with the ability to work independently.
Preferred Qualifications-
Leadership capabilities.
Experience with analog design / back-end for analog design.
Experience with RF design / back-end for RF design.
Experience with Synopsys tools.