לוח משרות דרושים FPGA משרה מלאה, לחיפוש זה נמצאו 19 משרות

​If you are looking to make an impact, come and join a team developing the next generation of space communication technology.
Our mission is to revolutionize the way satellites, space robots and spacecrafts communicate through deep space, in earth orbit and with ground stations. Our technology is based on space proven state-of-the-art proprietary architecture that enables a different approach to the way space communication systems are designed.
We are looking for experienced FPGA Engineers to lead innovation in the next generation space connectivity technology.
What you will be doing​:
Design and manufacture systems including ICs by RS and SoC type FPGAs
Design and implement high-speed digital signal processing algorithms.
Design for highly robust, distributed systems with emphasis on managing physical effects that originate from the harsh space environment.
Implement DSP algorithm on SoC type FPGAs.
Key contributor to Digital, Modem architecture and design.
Lead technical reviews with key stakeholders.
Work closely within a multi-disciplinary team to lead high-impact technical decisions about system design, implementation, and verification.

We are looking for an experienced FPGA Design Engineer who will play a pivotal role in developing , designing and optimizing FPGA solutions for our cutting-edge projects. Your expertise will drive innovation and excellence in digital design as part of the detection team in CT\AMI.
Your role :
Develop FPGA logic using VHDL / Verilog
Design and implement high-speed data paths and interfaces such as DDR, PCIe, Ethernet.
Perform simulation, verification, timing closure, and debugging
Integrate FPGA with soft processors (such as MicroBlaze / Nios), sensors, ADCs/DACs, and other system components
Support system bring-up, lab validation, and debugging at both board and system level
Collaborate closely with hardware, firmware, software, and system teams
Support and participate in architecture discussions and design reviews
Read and understand board schematics to support integration and troubleshooting
Support digital component replacement activities, including identifying alternatives and validating implementation impact
Perform lab and system-level testing after component changes or design updates
Document FPGA design, interfaces, and implementation details
Support release processes in PLM (Product lifecycle Management) system , including documentation updates and design release activities

Required Senior AI SoC Design Verification Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

we are looking for a Experienced Verification Team Leader - FPGA/ASIC.
Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.
Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station
Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs

Required Senior SoC Design Verification Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Senior CPU Design Verification Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required CPU Design Verification Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Senior Verification Engineer (FPGA)
Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment - those who want to be part of the next generation of airspace security innovation.
Join us and help make the world a safer place.
Work with the worlds leading cyber-takeover counter-drone technology provider and shape the future of safe airspace.
Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.
Key Responsibilities:
Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.

We are looking for a hands-on FPGA Design Engineer, specialized in high-performance digital design and FPGA-based system development, as part of the Platform team.
This role involves ownership of FPGA interfaces and connectivity logic, including high-speed communication blocks, platform integration, and close collaboration with embedded and hardware teams. You will work on complex FPGA/SoC platforms, enabling robust and scalable solutions for quantum control systems.
Responsibilities:
Own the design and implementation of FPGA-based interfaces such as PCIe, I2C, SPI, and high-speed GT communication.
Develop and integrate FPGA logic on advanced platforms, including Xilinx UltraScale+ and Versal.
Collaborate closely with embedded, hardware, and system teams to ensure seamless HW/SW/FPGA integration.
Drive FPGA bring-up, debugging, and validation at both lab and system levels.
Participate in system architecture definition and cross-team design decisions.

abra is seeking for an Senior FPGA Engineer This role require close collaboration with multidisciplinary teams, including hardware, software, verification, and system engineers, to deliver high-performance, mission-critical FPGA solutions—from concept and design through development and production, all the way to integration and operational deployment. Full-time position, Sunday–Thursday, in Holon.

We are looking for a motivated Principal FPGA Engineer to join our team in Raanana.
You will have the chance to develop your own skills in a flexible and energetic work atmosphere with friendly and experienced colleagues. You will have helpful supervision, opportunity to learn, modern tools and flexible work culture.
If you want to be a part of our growing company that is driven by innovation and is focused on building a future together with our employees, consider applying.
Principle duties and responsibilities :
Design and develop FPGA/ASIC solutions across the full product lifecycle, including feasibility studies, architecture definition, implementation, verification, and production support
Work independently to deliver high-quality engineering solutions with minimal supervision.
Operate at the system architecture level across multiple design domains.
Serve as a Subject Matter Expert (SME) in one or more technical areas and provide consulting to other teams.
Lead and contribute to complex, high-impact projects critical to the business.
Integrate AI tools in FPGA/ASIC development process.
Mentor and provide technical guidance to junior and senior engineers.