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we are looking for a Board Design Engineer to join a team developing advanced hardware solutions at the heart of cutting-edge defense technologies. This is an opportunity to take part in the development of mission-critical products, work with multidisciplinary teams, and make a real impact through innovative electronic design
In this role you will Own the full lifecycle of board design from requirements definition through architecture, design, and testing Design printed circuit boards that serve as core elements in advanced Elbit Systems products Work closely with Software, FPGA, Mechanical, and additional engineering teams throughout the development process Take part in the development of complex digital electronic systems in a highly technological environment Contribute to solving challenging engineering problems and advancing robust, high-performance hardware solutions
Requirements Bachelors degree in Electrical Engineering At least 7 years of experience in digital electronic design Experience in board requirements definition and top-level architecture definition Proficiency in PCB design tools such as Altium Designer, Mentor Expedition, or Cadence Knowledge of PCB layout methodologies and signal integrity tools such as Hyperlynx or Ansys Experience in Voltage Regulated Modules (VRM) design and analog circuit design - Advantage Experience with processor-based hardware platforms, CPU architecture such as ARM or X86, and system -level design - Advantage Knowledge of Python or other software languages, strong problem-solving skills, and ability to work effectively with multidisciplinary teams
Only relevant applications will be answered #Modiin-Maccabim-Reut

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment with the focus on the following goals.

Deep understanding of components/modules within wireless communication systems and the corresponding calibration and impairment reduction techniques - Develop methods/algorithms to alleviate hardware induced impairments by calibration, cancellation and other applicable techniques - PHY firmware architecture and design, including calibrations, real-time processing flows, collaboration with RF hardware, microcode, and MAC layer.

Develop highly efficient designs delivering outstanding performance, optimizing power and memory footprints while meeting hard-realtime latency requirements.

Debug real-time systems with limited visibility, working hands-on with development boards and lab equipment.

Collaborate with Radio, MAC, and Systems engineering teams to architect, define and implement innovative algorithms, calibrations, and protocols.

Support pre-silicon validation efforts, including simulation, emulation, and FPGA prototyping.

Develop SoC test and calibration capabilities for chip, module, and product factories.

Support post-silicon bringup, validation, performance characterization, system integration and debugging. - Repeatedly measure and optimize results using various test harnesses - Automate calibration and verification processes.

Required Integration Engineer
Job Description:
Join our multidisciplinary integration team and take part in the development and validation of advanced RF-based systems. The role involves hands-on work with complex hardware and software systems, prototype setup and testing, troubleshooting, and close collaboration with multiple R&D teams.
Responsibilities include:
Integration and testing of complex multi-module systems
Involvement throughout the full development lifecycle of RF and digital systems
Setup and validation of prototype systems at both hardware and software levels
Identifying hardware/software issues and driving technical solutions
Working closely with software, hardware, and final testing teams
Participating in challenging, development-oriented projects with strong growth opportunities.

Required Senior SoC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Contribute to test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Staff Design Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Our Autonomous Driving group is looking for a system integration engineer to join our growing team!
You will play a key role in designing and developing AV platforms, and should be comfortable with defining complex system architectures and hands-on bring-up, debug, and prototyping.
The system integration team ensures fast & successful enablement of our AV platforms, from design phase to product launch, while collaborating with internal & external stakeholders. We're looking for a strong, hands-on, System Integration Engineer who is passionately motivated by challenges and excels in troubleshooting complex problems.
What will your job look like?
Accompany the product development from the early design stages (block diagram, schematics, layout, SI/PI/TA simulations), reviewing and approving the hardware design, towards the board bring-up and approval.
Collaborate with multi-discipliner (HW/SW/System) development teams, in order to ensure the product success prior customer delivery.
Responsibility for providing quick and professional analysis and troubleshooting of advanced issues.
Have the opportunity to work on innovation, including initiating and developing tools to enhance the team's work efficiency.

We are seeking a software engineer to build high-performance software models of advanced SoC designs and to help bridge the gap between Software and Hardware, influencing performance improvements, power efficiency, security, and the programming ease of Apple products.
Responsibilities
In this role, you will:
Develop software systems and tools used to bring up the future OS on future SoCs.
Support kernel and driver development on future processor & SoC models.
Work closely with software and hardware teams across product and research groups.
Promote new opportunities and techniques with other groups.

The Labs Security Team secures the firmware at the foundation of our custom silicon. We work on Graviton processors and the Nitro System - hardware that runs a substantial share of the world's cloud workloads - in close collaboration with the silicon architects and firmware developers who design it. Our engineers operate at the lowest levels of the stack: secure boot chains, hardware root of trust, attestation, cryptographic protocol design, and the boundaries between trust domains within the system.

Key job responsibilities
As a Security Engineer, you will threat model new silicon and firmware architectures, conduct low-level penetration testing against privileged and externally reachable interfaces, review designs and code across multiple firmware components, and build the fuzzing and analysis tooling that makes this work repeatable at silicon scale. You will also help raise the security bar across the wider organization through direct engagement with firmware and hardware teams. We are looking for engineers fluent in C and ARM assembly, with real depth in secure boot, applied cryptography, or embedded exploitation, and the technical credibility to hold a position in a room full of people who designed the system you are testing.

We are looking for a Senior Chip Design Engineer to join our Network Adapter Silicon group. As a Senior Design Engineer in our Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Own micro-architecture definition and RTL implementation of chip blocks/entities according to specifications, performance, timing, area and power requirements.

Drive your design through the full implementation flow - synthesis, timing closure, lint/CDC and physical design constraints - together with the backend teams.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, Verification, FW and Post-Silicon validation.

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.
We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities
Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

Our R&D team develops one of the companys leading products and is involved in the design and development of advanced Linux-based networking solutions.
We are looking for a talented Development Engineer to join our team and take part in building innovative software solutions in a dynamic and challenging environment.
Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing our groundbreaking and innovative chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:

Join the Tel Aviv or Beer-Sheva group, working on RiscV processors platform.

Verification for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.

Daily work might involve any or all aspects of chip development including verification, integration, debug

Work closely with firmware and other groups around the globe.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.