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we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

Required Logic Design Engineer
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.

we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You wont just be using tools; youll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.


Key Responsibilities

Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows

We're looking for a talented SoC Integration Lead to join our Nitro team and help shape what comes next. You will spearhead the SoC integration activities of sophisticated networking chips, collaborating closely with Architecture, RTL Design, Physical Design, Package Design, Verification, Software, DFT, and additional teams in a dynamic, open, and fast-paced environment. As a member of the Nitro project, you will have influence over the device through its entire lifecycle from product definition to mass production. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries.

Key job responsibilities
Take full ownership of SoC integration, including IPs development, partitioning, clock domain crossing (CDC), reset domain crossing (RDC), exploratory synthesis, and design quality verification.
Drive chip-level design implementation by partnering with multiple teams including Architecture, RTL Design, DFT, Verification, System Verification, STA, and Physical Design.
Oversee the creation of SoC-level IP blocks such as fabrics, interfaces, and security modules.
Lead RTL integration activities including micro-architecture definition, RTL coding and debug, synthesis and timing closure, and sign-off.
Address diverse functional and structural challenges, encompassing functional debugging, physical design preparation, emulation, and design quality issue resolution.
Contribute to the creation and implementation of design flows and automated solutions that facilitate efficient SoC development.
Support Verification and Emulation teams through test plan development and coverage review.
Ensure the chip meets quality and reliability standards while delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders.

We are looking for an experienced Senior Fuse Configuration Manager for the IC Product Engineering organization, responsible for fuse configuration management across all our Networking products. You will drive execution and scheduling of all fuse-related configuration aspects across our Networking teams while aligning with corporate priorities, constraints, and methodologies.
We are a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer best-in-class solutions that include adapter cards, switches, cables, and software to support networking technologies. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. We serve a wide range of sectors including high-performance computing, enterprise, data centers, cloud computing, big data and Web 2.0. Our product line focuses on delivering the most optimized Ethernet solutions for industries like Media and Entertainment as well as any other industry that can benefit from our Datastream and TCP/IP acceleration.
What you'll be doing
Coordinate between all project collaborators such as Chip Design, Q&R, Architecture, ICPE, and others from initial fuse definition stage through product end-of-life, including release to mass production.
Own and manage all fuse CCB (Change Control Board) activities.
Collaborate closely with domain owners and stakeholders across various teams to gather and validate inputs required for product fuse configuration, ensuring alignment with overall project and product strategies.
Manage and coordinate configuration files and parameters for multiple products, maintaining accuracy, traceability, and consistency throughout the product lifecycle.
Contribute hands-on to product execution activities by actively working on configuration management, including updates, troubleshooting, and validation of fuse-related configuration settings.
Support the integration of product fuse configurations into the overall product development, test, and manufacturing processes, ensuring smooth deployment and operational readiness across multiple product lines.

We are seeking an exceptional architect to join our architecture team and shape the future of quantum control. We have a unique opportunity to shape the architecture of next-generation quantum computers toward utility-scale quantum computing.
In this role, you will define the logic architecture of the devices that are the heart of the next-generation quantum control platform. Designing the devices, including the pulse processor and their interfaces, requires a deep understanding of quantum computing, the system tradeoffs, and product requirements.
In this role, youll collaborate with Product and with the other members of the architecture team to define the requirements and the roles and responsibilities of each component. Youll identify system-level tradeoffs and identify solution alternatives. Youll work closely with the logic design and compiler teams to define a winning architecture.
Responsibilities: 
Architecture for the next-generation quantum control platform devices, ASIC, and logic components.
Define system-level architecture and features, providing detailed specifications to the various R&D teams.
Collaborate with the product and research teams to transform high-level requirements into architecture and spec definitions, and present tradeoffs.
Work with partners and vendors on requirements, integration architecture and joint development to optimize the product capabilities.

We are looking for you to join our emulation team focusing on the creation, deployment, and support of advanced emulation environments. In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly.

As a senior emulation engineer, you will have the responsibilities as follows: Work closely with emulation, architecture and verification teams to create and enhance emulation environments. Work with the leading emulation vendors to debug issues and deploy new capabilities. Develop new emulation workloads and platforms to enhance user productivity . Develop high performance emulation models and transactors in system Verilog and C/C++ . Support multiple emulation environments using the latest emulation techniques Root cause failing SoC/Processor tests and emulator environment issues.

We are seeking a highly skilled and versatile Performance Research and Analysis Manager to join our Performance Group. This role will drive end-to-end performance strategy and execution for next-generation NIC, Switch, and Networking technologies, spanning the full lifecycle from pre-silicon performance modelling (simulation and emulation) through bring-up, validation, and GA readiness. The ideal candidate will lead cross-functional performance efforts across multiple teams to evaluate and optimize low-level networking and offload capabilities, including Storage acceleration, Security protocols, NIC pipeline and steering mechanisms, Switch performance, and E2E AI Networking cluster level performance for AI WLs, distributed training, and Inference jobs.
In addition, this role will play a key leadership position in building scalable telemetry frameworks, performance dashboards, and job-level monitoring solutions to enable continuous performance tracking and root cause analysis across our supercomputing environments. The position also includes deep ownership of competitive benchmarking and performance analysis. You will work closely with a wide range of our hardware and software platforms, including HCAs, DPUs, switches, CPUs, GPUs, and full system architectures, across multiple networking stacks and performance-critical software layers.
What you'll be doing:
Lead performance research and evaluation of advanced networking technologies supporting AI workloads, including LLM training and inference at supercomputing scale.
Define end-to-end performance test plans and methodology for next-generation Networking HW and networking technologies, including performance expectations and target KPIs.
Drive benchmarking, profiling, reporting, and deep performance characterization of networking workloads and offload features.
Collaborate closely with simulation, architecture, chip-design, firmware, and software teams to assess performance tradeoffs and identify bottlenecks.
Perform deep root cause analysis (RCA) for performance gaps and stability issues, and drive cross-team mitigation plans.
Develop and enhance performance analysis tools, automation frameworks, and scalable methodologies for cluster-level performance evaluation.
Own performance observability efforts, including telemetry pipelines, dashboards, and job-level performance analytics.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.



Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!



What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

we are a leading semiconductor design center, developing SoCs, microcontrollers, and security hardware solutions for tier-1 customers in the computing and server space. As a self-contained R&D center - spanning architecture, chip design, software, and system engineering - we work closely with major US-based OEMs to deliver innovative, semi-custom silicon solutions. We are now extending our portfolio into AI acceleration, developing a next-generation NPU platform aimed at efficient, real-world AI deployment.
?Shape the Future of AI at the Silicon Level We are looking for a visionary Senior Technical Manager to build and lead our AI software stack for our next-generation NPU platform This is a rare opportunity to own the full software layer - from compiler infrastructure to Developer ecosystem - and make a lasting impact on how AI runs on silicon. What You'll Do; Build and lead a highly skilled AI software & algorithms engineering team, establishing engineering standards, development processes, and technical direction Define the end-to-end stack - compiler, runtime, Kernel libraries, and SDK - enabling efficient AI deployment on our NPU Drive AI compiler development using technologies like MLIR, TVM, LLVM or similar infrastructures to translate PyTorch/TensorFlow models into optimized NPU execution Champion model optimization - quantization, pruning, and hardware-aware techniques for maximum performance and power efficiency on the accelerator. Runtime, Drivers, and Firmware Integration - scheduling, memory management, and low-level software for AI workloads on-chip AI Kernel Libraries - Guide the development of highly optimized neural network Kernel libraries and performance-critical primitives tailored to the architecture of the NPU. Developer Ecosystem - Define and deliver the SDK, APIs, and development tools that allow internal teams and external developers to deploy AI models easily on the platform. Cross-Functional Architecture Collaboration - Work closely with silicon architecture and hardware design teams to ensure optimal hardware-software co-design, providing feedback on architecture, performance bottlenecks, and future ISA requirements.

In this highly-visible role you will assume responsibility over a full range of DFT in an extremely challenging project, leading a talented team of engineers, working closely with frontend and backend teams. You will participate in architecture and design reviews, create design solutions for testability, debug ability, reliability and yield improvement. You will provide design constraints for implementation and sign-off. You will build work plans, drive and track their execution. You will be closely involved in silicon bring-up, reliability testing and advanced physical failure analysis activities, and will be responsible for getting a high-quality product out into AWS fleet for millions of our customers quickly. Come and join us as we work hard, have fun, and make history.

We are looking for an experienced, talented CPU ASIC front-end design expert and technical lead. In this role, you will take part in developing cutting-edge high performance best in class RISC-V CPU, from definition stage through planning stage and the development of new features while solving challenging implementation problems and ending in successful tape-out and product bring-up.

Responsibilities
Learn high performance RISC-V Arch and algorithms.
Define and drive the design of advanced and super complexed blocks from micro-architecture phase to tape out.
Work closely with various teams to drive execution (SW, Architecture, verification, BE, FPGA, postSi etc).
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making.

we are a global leader in hybrid control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software offer a groundbreaking approach to controlling quantum computers, scaling from individual qubits to arrays of thousands.
For this role, we are looking for an R&D Software Engineer individual who is both an experienced engineer and a great people person.
Someone who can evaluate existing workflows, devise and communicate new solutions, own and deliver them, taking our company to the next level.
Responsibilities:
Actively investigating, understanding, and challenging workflows in the company, interacting daily with software and hardware engineers.
Continuously suggesting and delivering new ideas to enhance and improve our products and the work of engineering teams.
Driving the adoption of AI capabilities and modern practices across chip design, verification, and software teams.
Partnering with engineering teams to plan, develop, and deliver high-quality software infrastructure in a complex hardware + software environment.

Want to get your hands on our cutting edge Switching technologies? Switch Firmware team is looking for a Senior Firmware engineer to take part in the architecture definition of the Firmware / HW interfaces of next generation state of the art Switch products.
What you'll be doing:
As a Firmware engineer in the position of micro-architecture, you will work closely with the various chip design teams and define the Firmware architecture for all the features developed in the Firmware team. This role offers you an excellent opportunity to accomplish something new, enable deep and thorough understanding of the HW and Firmware in a rapidly growing field while solving exciting technical issues for improving next ASIC generations.

we are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities:

Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.