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2 ימים
דרושים באלביט מערכות
מיקום המשרה: לוד
סוג משרה: משרה מלאה
לאתר החברה באירפורט סיטי דרוש.ה מהנדס.ת מערכת חשמל

לחברת אלביט קינטיקס הממוקמת באירפורט סיטי ועוסקת בפיתוח וייצור מערכות אנרגיה, קירור ומיזוג אויר
דרוש.ה system Engineer לפיתוח מערכת מולטידיסציפלינרית ( חומרה, תוכנה, מכני)

תיאור התפקיד:
אפיון וכתיבת דרישות למערכת מולטידספלינרית הכוללת חומרה, תוכנה, ממשקי תקשורת
התפקיד כולל ראיה מערכתית מקצה לקצה, הגדרת דרישות טכניות
לווי הפרויקט לאורך כל חיי מחזור חייו משלב האפיון ועד למסירה ללקוח
אינטגרציה מערכתית system integration ובדיקות מערכת system verification
כתיבת מסמכי מערכת, תרשמי זרימה, סכמת בלוקים ומפרטי ממשקים
זיהוי וניתוח סיכונים עמידה בסטנדרטים איכות ובטיחות
השתתפות בסקרים טכניים Design Review והצגת תוצרים מול גורמים פנימיים וחיצונים
ממשק מול לקוחות וצוותים טכניים חיצוניים
דרישות:
תואר ראשון Bsc בהנדסת אלקטרוניקה - חובה
לפחות 3 שנות ניסיון בפיתוח מערכת מולטי-דיסציפלינרית ( חומרה, תוכנה ומכניקה) חובה
ניסיון עם מערכות Power Electronics - עדיפות גבוהה
Hands On עבודות חשמל, פירוק מכללים, הובלת בדיקות ואינטגרציה באתר החברה, אתרי לקוח, עבודה בשטח
ניסיון קודם כטכנאי.ת/ הנדסאי.ת עדיפות גבוהה
ניסיון בכתיבת מסמכי אפיון מערכת, שרטוט סכנות חשמליות
שליטה באנגלית טכנית ברמה גבוהה (קריאה, כתיבה ודיבור)

כישורים נוספים
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יצירתיות וראיה מערכתית
עצמאי.ת בעל.ת יכולת תיעדוף משימות
ידע הנדסי רחב
סקרנות
יכולת עבודה תחת לחץ ועמידה בלוחות זמנים מאתגרים.

*רק פניות מתאימות ייענו המשרה מיועדת לנשים ולגברים כאחד.
 
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משרה בלעדית
2 ימים
Location: Rehovot
Job Type: Full Time and Hybrid work
What you'll be doing?
- Design systems which are a mix of state-of-the-art optics, scanning electron microscopes, lasers, motion systems, control, signal & image processing, advanced algorithms and software
- Define and validate system & modules technical requirements , seniors will lead complex sub system or the full product as a chief system Engineer
- Perform complex experiments to set the path towards next-generation solutions, look at the best solution architecture of our products
- Troubleshoot and solve a wide range of problems
Requirements:
- B.Sc in Physics / Electrical Eng (MSc - advantage)
- 5+ years of multidisciplinary systems R&D
- Experience as a professional Developer in SW/ Algo/ Physics/ Motion in multidisciplinary R&D - advantage
- Experience as an R&D Project management in multidisciplinary project - advantage
- Firm background in electro-optics, control theory or signal/image processing
- Solid knowledge of data analysis and signal/image processing using Python or Matlab
- Strong problem solving and troubleshooting skills
- Strong English oral and written communication skills, presenting skills
This position is open to all candidates.
 
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8555221
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משרה בלעדית
2 ימים
Location: Rosh Haayin
Job Type: Full Time
A company in Rosh HaAyin is recruiting
Senior RF Engineer | Antennas RF Systems
The role includes
Design and develop antennas and antenna arrays for advanced RF applications
Develop RF circuits and support transition from R D to production
Perform EM simulations using HFSS and CST
Use Python and/or MATLAB for RF analysis, automation, and optimization
Lead multidisciplinary projects involving RF and digital systems
Work closely with system, digital, mechanical, and manufacturing teams
Requirements:
7+ years of experience in antenna and RF circuit development
Strong hands-on experience with HFSS and CST
High-level proficiency in Python and/or MATLAB
Proven experience leading multidisciplinary RF + Digital projects
B.Sc./M.Sc. in Electrical/ Electronics Engineering or equivalen
This position is open to all candidates.
 
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8513467
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דרושים בNishapro
Job Type: Full Time
Located in Tel Aviv

Responsibilities:
1st Technical contact for development quality departments linked to assigned customers in Europe
Establishing excellent network within customers engineering organization foster vital exchange
Present promote on a regular base product roadmaps to increase BOM utilization
Drive Demand Creation Design-in process across product portfolio
Initiate technical initiatives to find new biz opportunities in conjunction with customer package teams
Collect intelligence of customers needs to support portfolio steering eliminating gaps
Develop catch new Business opportunities prepare floor to participate on upcoming RFQs
Handling and managing of product database and update regularly on innovations
Requirements:
Engineering related major (Preferred if has knowledge in semiconductors and IC packaging)
At least 2~3 years of experinece in technical sales, engineering
Strong handling in MS office (Excel, PowerPoint presentation)
Customer oriented mind
Structured, responsible, independednt and proactive way of working
Strong communication skills, presentation skills, reporting skills
Fluent in English are needed
This position is open to all candidates.
 
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8469449
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
2 ימים
דרושים בRisco Group
Location: Rishon Letsiyon
Job Type: Full Time
Lead the Core Embedded Platform Behind Our Devices
We are looking for an experienced Embedded Linux Group Leader to lead our Embedded software organization responsible for the core firmware and system software powering our next-generation devices.
You will lead multiple Embedded Linux teams (10+ engineers), including remote developers, and take ownership of the Embedded architecture across products. This is a high-impact leadership role combining technical vision, system architecture ownership, and people management in a global environment.
Requirements:
10+ years of Embedded software development experience
5+ years in leadership roles managing teams (including remote teams)
Strong experience designing and building Embedded Linux architectures
Deep expertise in:
o C ++ (strong hands-on capability)
o Linux user space and Kernel space
o Device drivers and Kernel modules
o Bootloaders (e.g., U-Boot)
o Yocto / Buildroot
Good knowledge of JAVA (advantage)
Experience with board bring-up and hardware/software integration
Strong understanding of communication protocols (I2C, SPI, UART, USB, etc.)
Proven experience troubleshooting complex low-level system issues
Experience working in a global or distributed organization
This position is open to all candidates.
 
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8576772
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דרושים בגב מערכות
מיקום המשרה: תל אביב יפו
סוג משרה: משרה מלאה ועבודה היברידית
לחברת טכנולוגיה בתחום ה-Retail Tech המפתחת פלטפורמה מתקדמת לניהול רשתות מזון וקמעונאות - דרוש/ה מפתח/ת בכיר/ה מוביל/ה (Hands-On Lead) להצטרפות לצוות פיתוח חזק ואיכותי.

החברה מפתחת מערכת ליבה רחבה המספקת לרשתות מזון מעטפת מלאה:
ניהול הזמנות, משלוחים, עובדים, לקוחות, מלאי בזמן אמת, לוגיסטיקה, עלויות, שיווק ותפעול - כולל אפליקציות וממשקים ניידים לכל עובד בארגון.

מה בתפקיד?

הובלה טכנית של פיתוח פיצרים מקצה לקצה
עבודה Hands-On ברמה גבוהה ( frontend דומיננטי)
תכנון פתרונות, ארכיטקטורה וחיבור בין Client, backend, DB ו-Cloud
אחריות על Ticket Design, Code Reviews וסטנדרטים מקצועיים
שותפות אמיתית בבניית המוצר והכיוון הטכנולוגי
הובלה מקצועית של מפתחים נוספים בצוות
דרישות:
דרישות חובה
ניסיון של 5+ שנים בפיתוח תוכנה ( frontend + backend )
ניסיון משמעותי ב- React - חובה
ניסיון ב- React Native - יתרון משמעותי
ניסיון בתכנון והובלת פיצרים מורכבים
הבנה עמוקה בארכיטקטורה ומערכות מבוזרות
ניסיון בעבודה עם REST APIs, DB ו-Cloud
ניסיון בעבודה בצוות, Code Review ו-Best Practices
יכולת הובלה, אחריות וראייה מערכתית רחבה

יתרון משמעותי
ניסיון בפיתוח ב-Go (Golang)
עבודה עם WebSockets ו- Real-Time Systems
Docker / Kubernetes
עבודה עם GCP
ניסיון במערכות Retail / Ecommerce / CMS
ניסיון בעולמות Mobile המשרה מיועדת לנשים ולגברים כאחד.
 
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8475013
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
דרושים בוייזדום
Job Type: Full Time
Deep-tech startup developing advanced sensing and AI systems is looking for a Senior Algorithm engineer to join the core team.
This role is aimed for strong algorithm engineers who enjoy developing end-to-end solutions in multidisciplinary environment from research to production.
Responsibilities
Lead the end-to-end development of Real-Time algorithms for sensing systems.
Work with complex data modalities such as video, audio, points cloud and other signals
Develop algorithms that generate reliable Real-Time insights from noisy real-world data
Design and build autonomous decision-making systems
Drive experimentation, system optimization and data collection
Work closely with a multidisciplinary engineering team
Requirements:
3+ years experience developing algorithmic systems for real-world applications
(sensing, robotics, signal processing, decision systems - strong advantage)
Hands-on experience in signal processing - must
(physics signals / video / audio / points cloud)
Strong programming skills - Python and/or C ++
Background from elite technological units or strong deep-tech companies - advantage
Ability to independently drive complex problems end-to-end
Stable employment history and strong professional track record
BSc in Electrical Engineering / Physics / Computer Science or similar
Additional Details
Full onsite role - 5 days from the office (Yigal Alon, TLV)
Fast-moving startup environment with high technical ownership
Work on cutting-edge sensing and AI technologies used in defense, civilian and industrial domains
This position is open to all candidates.
 
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8580781
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חברה חסויה
Job Type: Full Time and Hybrid work
A global technology leader in IoT-based platforms for security, healthcare, and senior care markets. With over 80 million devices deployed worldwide, our mission is to deliver innovative, cloud-connected solutions that empower people to live safer, more independent lives. Our products span smart home security, health monitoring, and emergency care-developed and manufactured in-house, from device to cloud.
We are seeking a Senior Embedded Engineer to join our team in our offices in Herzliya.
Requirements:
Bachelor's degree in Computer Science, software engineering, or a related field from a leading institute.
At least 5 years of hands-on experience in Real-Time Embedded software development in C.
Strong proficiency in C programming for Embedded systems.
Proven experience developing firmware on microcontroller-based systems, preferably ESP32-class or ARM Cortex-M devices, using FreeRTOS or Bare Metal.
Hands-on experience with Agentic AI frameworks, including autonomous systems, decision-based intelligence, or context-aware agents.
Ability to integrate AI capabilities into software development processes, including design, coding, and problem-solving.
Strong analytical mindset and ability to identify opportunities to enhance development efficiency and product quality using AI-driven insights.
This position is open to all candidates.
 
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 
משרה בלעדית
2 ימים
סוג משרה: משרה מלאה
Senior Design Engineering Manager data Centers

להובלת תחום התכנון וההנדסה בפרויקטי דאטה סנטר מורכבים.

התפקיד מתמקד בהובלת תכנון מערכות בדגש חשמל, תוך אינטגרציה עם מערכות מכאניקה, בקרה ו BIM, בשיתוף פעולה עם מרכז הנדסה בינלאומי.

תחומי אחריות

הובלת תהליכי תכנון מקצה לקצה משלב קונספט ועד תכנון מפורט.

ניהול ממשקים מקצועיים מול לקוחות, יועצים ומתכננים.

הובלת תיאום מערכות רב תחומי בין חשמל, מכאניקה, בקרה ו BIM.

שמירה על סטנדרטים הנדסיים גבוהים ואחידות בין פרויקטים.

עבודה שוטפת מול מרכז הנדסה גלובלי לצורך השלמת דיסציפלינות הנדסיות.

ליווי הפרויקטים בשלבי התכנון ומתן מעטפת הנדסית ברמה גבוהה.
Senior Design Engineering Manager data Centers

We are looking for a senior engineering leader to join a global organization and lead Design Engineering activities for complex data center projects.

This role focuses on electrical led
דרישות:
דרישות
תואר בהנדסת חשמל או מכונות חובה.
ניסיון בתפקידי Design Engineering בפרויקטים מורכבים חובה.
רקע מחברות תכנון או תפקידי תכנון הנדסי חובה.
הבנה רב תחומית במערכות חשמל, מכאניקה ובקרה.
ניסיון בעבודה מול לקוחות, יועצים וממשקים מרובים.
ניסיון בפרויקטי דאטה סנטר יתרון משמעותי, לחלופין ניסיון בתשתיות קריטיות כגון אנרגיה, בתי חולים או מתקנים מורכבים.
היכרות עם BIM יתרון. המשרה מיועדת לנשים ולגברים כאחד.
 
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הגשת מועמדות
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8585454
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
 
משרה בלעדית
2 ימים
דרושים בתדהר בנייה
מיקום המשרה: מספר מקומות
סוג משרה: משרה מלאה ומתאים גם לסטודנטים
קבוצת תדהר מזמינה אותך להצטרף ליחידת ה-  VDC (Virtual Design and Construction) בה אנחנו לא רק מתכננים בניינים; אנחנו מייצרים Digital Twins ומשנים את הדרך שבה ישראל נבנית.

מה מחכה לך אצלנו?
הובלת תהליכי תכנון לייצור (DfMA) בשיטת BIM - הפיכת מודלים למציאות ברמת דיוק גבוהה
מתן פתרונות יצירתיים לאתגרים הנדסיים מורכבים, עוד לפני תחילת הביצוע בשטח
עבודה שוטפת עם יועצים, צוותי ביצוע וקבלנים, והובלת החיבור המקצועי בין תכנון לביצוע
אחריות על מספר פרויקטים במקביל, ניהול ותחזוקה של מודלים מורכבים והובלת סטנדרט איכות חדש
דרישות:
מה אנחנו מחפשים?
מהנדס/ת אזרחי/ת בתחילת הדרך או סטודנט/ית בשנה ד' (עם יכולת ל-4 ימי עבודה בשבוע) - הזדמנות להתחיל בתפקיד משמעותי כבר במהלך הלימודים
זיקה טכנולוגית, יכולת למידה מהירה ורצון לעבוד בסביבה דיגיטלית מתקדמת
ניסיון קודם ב- REVIT  יתרון משמעותי (בסיס טוב הוא כל מה שצריך, את השאר נלמד יחד)
זמינות למשרה מלאה, עם גמישות לסטודנטים/ות לקראת סיום התואר המשרה מיועדת לנשים ולגברים כאחד.
 
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משרה בלעדית
2 ימים
חברה חסויה
Location: Omer
Job Type: Full Time
Based in the Omer Industrial Park (Omer, Israel), we are the SPHERA development team. Our mission is to build the world's most advanced simulation platform for robotics and autonomous systems.
What You'll Do (Key Responsibilities)
Design, develop, and maintain core features for the SPHERA simulation platform using C ++.
Work across the " Full Stack " of our simulation environmentfrom backend physics and systems integration to frontend UI / UX in-engine.
Integrate third-party hardware (like drone autopilots) and software (like ROS2) into the simulation.
Collaborate closely with a small, senior team on architectural decisions, code reviews, and problem-solving.
Optimize code for Real-Time performance, scalability, and high-fidelity accuracy.
Travel to client sites to provide on-site Technical Support, integration assistance, and product demonstrations.
Requirements:
A Bachelor's degree in Computer Science, Computer Engineering, or Information Systems Engineering.
At least 3 years of professional software development experience in C ++.
A strong background and comfort working in a Linux environment.
Proven ability to work effectively as part of a team, with strong communication and collaboration skills.
A highly organized and methodical approach to development, testing, and documentation.
Willingness and ability to travel internationally to meet with clients for support and integration.
Must be able to work full-time from our office in Omer (this is not a remote position).

What Will Set You Apart (Beneficial Knowledge)
Hands-on development experience with Unreal Engine 5 (UE5).
Hands-on experience with ROS2.
This position is open to all candidates.
 
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2 ימים
דרושים בRisco Group
Location: Rishon Letsiyon
Job Type: More than one
We are looking for a hands-on Senior Priority & BI Developer to support and develop our enterprise systems and business applications.
You will own development, implementation, integration, and ongoing optimization of the organizations enterprise information systems, with a strong focus on Priority ERP and BI.
The role includes hands-on involvement in cross-organizational processes, from requirements analysis and system design, through development, implementation, and ongoing improvements aligned with business and operational needs in a manufacturing environment.

Responsibilities:
ERP system Ownership (Priority) - Lead end to end process analysis, customization, and development within Priority ERP. Translate operational and manufacturing needs into system design, custom solutions, and ongoing optimization.
BI Development - Develop analytical models, dashboards, and
Requirements:
7+ years of experience in information systems development including BI systems, Priority and CRM
Experience in a manufacturing organization - Advantage
Strong understanding of business and organizational processes
Deep knowledge in Priority ERP - development and implementation
Strong familiarity with information system architectures
Good knowledge of automation tools (e.g., n8n, SSIS)
Experience working with REST APIs
Experience with ETL processes
Strong knowledge of SQL query writing
English - very high proficiency
This position is open to all candidates.
 
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10/02/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Act as Partition/Unit level physical design technical leader and focal point.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

5+ years of experience in physical design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.
This position is open to all candidates.
 
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3 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Knowledge in Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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10/02/2026
Location: More than one
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering.

You should have at least 5+ years of hands-on layout experience, demonstrating your proven expertise.

A strong background in Physical Verification methodology, including ERC, LVS and DRC, is necessary.

In-depth knowledge of advanced silicon process technologies.

Familiarity with physical build EDA tools, including Synopsys and Cadence.

A great teammate who thrives in a collaborative environment.

AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:

Experience in Linux environments.

TCL, Python, shell scripting abilities.

Experience with data collection and analysis.

Understanding of the chip and die verification process.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. You will develop/define design options for performance, power and area.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog).
Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SoC-level.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience in logic design and debug with Design Verification (DV).
Experience with microarchitecture and specifications.
Preferred qualifications:
Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with design sign off and quality tools (Lint, CDC, VCLP etc.).
Experience in a scripting language like Python or Perl.
Knowledge of SoC architecture and assertion-based formal verification.
Knowledge of one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.
Knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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24/02/2026
Location: Haifa
Job Type: Full Time
Chips Talk, We Listen
we are a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we depend on computing systems daily. But how can we guarantee their safety, reliability and functionality? we are the first-ever company to provide visibility into next-gen chips while they are operating, based on the power of on-chip monitoring, machine learning, and data analytics.
Here at our company, you'll be part of a team that's unlocking deep insights to make electronics more reliable, efficient, and high-quality. We're trusted by industry leaders in data centers, automotive, communications, and consumer devices - we work with the world's largest and most notable companies in tech.
Why our company is a great place to work:
Fast-paced and impactful: We're a mission-driven startup, so you'll tackle new challenges daily, wear many hats, and see your work directly influence the future of electronics.
Supportive company culture: Learn from the best. Our 200+ team members are experts in their field with a proven track record of success, and they're committed to fostering a collaborative and supportive work environment.
International presence: We're a multinational company with a diverse team across multiple locations around the globe. You'll collaborate on projects with international impact, gaining a global perspective of the tech industry.
Work with industry leaders: Our solutions are used by the biggest names in tech. You'll be part of the team creating the next generation of groundbreaking products.
Cutting-edge playground: We use the latest machine learning, platforms, and tools to push boundaries and achieve breakthroughs.
Real-world impact: Our work keeps data centers, cars, and other critical systems running smoothly. Your work will directly contribute to safer, more reliable electronics.
We are here for the win: Backed by industry veterans and leading investors, we offer a stable and secure work environment with plenty of room for growth.
we are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.
Act as Functional Safety manager, leading the definition,
דרישות:
B.Sc. or M.Sc. in Electrical or Computer Engineering (or related field).
3+ years experience in SOC architectural roles
Technical knowledge: Strong understanding of SoC design flows, and system requirements.
Power and performance analysis: Ability to analyze and balance performance, power, and area trade-offs.
Strong system thinking - ability to move between micro-architecture depth and system-level abstraction.
Hardware and software collaboration: Proven experience working across hardware and software teams to achieve system goals.
Experience defining and documenting architecture specifications, interfaces, and integration flows.
Excellent communication and collaboration skills, with the ability to lead cross-functional discussions and influence stakeholders.
Experienc המשרה מיועדת לנשים ולגברים כאחד.
 
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Location: Giv'atayim
Job Type: Full Time
We are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of Nextsilison BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

Responsibilities:
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid.
Develop and validate high-performance, low-power clock network guidelines.
Perform critical block-level place and route and create designs that meet timing, area, and power constraints.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations.
Work with vendors on defining physical design methodologies and assist in flow development for chip integration.
Requirements:
7+ years of physical design experience, leading complex process designs.
In-depth knowledge of process and circuit design.
Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route.
Experience developing and implementing power-grid and clock specifications.
Good command of industry-standard physical design and synthesis tools.
Understanding of scripting languages, such as Perl and Tcl.
Working knowledge of extraction and STA methodologies and tools.
Good understanding of physical design verification methodology for debugging LVS and DRC issues at chip and block level.
Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power.
Leading projects and managing small groups: advantage.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving team behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define and drive the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering or equivalent practical experience.
4 years of experience with System on a Chip (SoC) cycles.
Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
Experience in high-performance, high-frequency, and low-power designs.
Preferred qualifications:
Masters degree in Electrical Engineering, or a related field.
Experience coding with System Verilog and scripting with Transaction Control Language (TCL).
Experience with Very Large Scale Integration (VLSI) design in SoC.
Experience with multiple-cycles of SoC in ASIC design.
Experience with layout verification and design rules.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how ASIC subsystem interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
Experience developing Register-Transfer Level (RTL) for ASIC subsystems.
Experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience working with software teams optimizing the hardware/software interface.
Experience working with design networking like: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience in Transmission Control Protocol (TCP), IP, Ethernet, Peripheral Component Interconnect Express (PCIE) and Dynamic Random Access Memory (DRAM) including Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
Experience architecting networking switches, end points, and hardware offloads.
Understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
Proficiency in procedural programming language (e.g., C++, Python, Go).
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, RTL coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power including low-power design techniques.
Experience with design sign off and quality tools (e.g., Lint, CDC, etc.).
Experience with SOC architecture.
Experience in logic design.
Preferred qualifications:
Master's degree or PhD in Computer Science or a related technical field.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate (DDR), Advanced Extensible Interface (AXI), or Advanced RISC Machines (ARM) processors family.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8544190
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead a complex ASIC subsystem and understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Implement designs in SystemVerilog.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience architecting networking ASICs from specification to production.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience working with software teams optimizing the hardware/software interface.
Proficiency in TCP, IP, Ethernet, PCIe, DRAM, Network on Chip (NoC) principles and protocols.
Proficiency in a procedural programming language (e.g., C++, Python, Go).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8544206
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25/02/2026
Location: Haifa
Job Type: Full Time
The Signal-Integrity & Packaging (SIP) team manages the external electrical interfaces of Annapurna Lab's chip devices, focusing on signal integrity, power integrity, and electrical usage.
The team collaborates with the BackEnd team to integrate interfaces into the die, designs package layouts for BGA substrates, and conducts signal and power integrity simulations. The team partners with the system team to develop optimal pin-out and PCB breakout schemes, performs electrical characterization of interfaces, and develops software tools for debug and diagnostics.

As a SIP team member, the scope of your work will be focused on Package substrate layout, with a blend of Signal & Power integrity extractions and simulations, as well as also influencing the DIE I/O structures.

Key job responsibilities:
Design and Layout of large and complex package substrates.
Understanding package substrate technologies and layout design rules.
Proficiency in Signal and Power Integrity considerations.
Layout test studies of Die bump-out structures and Package substrate breakout.
Layout test studies of Package pin-out arrangements and PCB board implementation.
Continuously improve the package design work, by coming up with initiatives that drive efficiency, and in turn help improve quality/cost/schedule of the package layout work.

The position is for an entry level, and we will teach and mentor all aspects of the role. No prior hands-on experience in the above list is required.
Requirements:
Basic Qualifications:
- BSc in Electrical Engineering, fresh graduate to 2 years work experience.
- General background in modern digital interfaces (e.g. PCI, DRAM).

Preferred Qualifications:
- Bachelor's degree in computer science or equivalent.
- Background in PCB layout, even as hobbyist.
- Attention to small details, striving for accurate and high-quality deliverables.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8560963
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Hod Hasharon and Haifa
Job Type: Full Time
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.
Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Solid understanding of general purpose CPU micro-architecture, including load store unit, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory technologies and memory controllers.
Ability to make trade-offs between power, performance and area to meet the requirements of the product.
Hand-on experience with high power-efficient CPU on chip interconnect, coherent fabric, memory controllers.
At least 8 years experience in architecture in one of the leading CPU companies
Experience modeling microprocessors using higher-level languages, like C/C++.
DESIRED
Co-operate and communicate well with the architecture and design teams.
Interact with the Product System architects, software teams and ASIC chip teams to define the overall architecture of the Processor ASIC including memory hierarchy.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8550286
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דיווח על תוכן לא הולם או מפלה
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תיאור
שליחה
סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Caesarea
Job Type: Full Time
The HW Board Design team is at the heart of our hardware development lifecycle, ensuring that every design is robust, testable, and ready for high-volume production. We bridge the gap between initial architecture and final qualification, playing a critical role in delivering high-quality networking solutions that power the internet. Our team is a collaborative group of technical experts who thrive on solving complex signal and power integrity challenges in a fast-paced, innovative environment. Joining this team means working on cutting-edge technology where your leadership directly impacts the reliability of global systems. We value a proactive, team-oriented mindset and a passion for engineering excellence.

Your Impact:
You will be responsible for leading hardware board design activities with a strong focus on test, qualification, and readiness for production. This role spans all phases of hardware development, from architecture and design through bring-up, validation, and qualification, combining deep technical expertise with leadership and cross-functional coordination.

Lead and mentor the hardware engineering team focused on board design, test, and qualification.
Define hardware architecture and board-level design strategy with test, qualification, SI, and PI requirements in mind.
Oversee schematic design, PCB layout, and component selection.
Review designs for quality, reliability, cost, manufacturability, testability (DFM/DFT), signal integrity (SI), and power integrity (PI).
Own test readiness, including support for bring-up, debugging, validation, and qualification.
Manage schedules, task prioritization, and resource allocation.
Work closely with FW, SW, mechanical, QA, test, and manufacturing teams.
Drive design reviews, SI/PI risk analysis, and technical decision-making.
Support transition from prototype to qualified hardware and production release.
Ensure compliance with relevant standards and qualification requirements.
Requirements:
Minimum Qualifications:
Bachelors degree in Electrical Engineering.
5+ years of experience in hardware board design and development.
3+ years of experience in a technical leadership or management role.
Proven experience with Signal Integrity (SI) and Power Integrity (PI) analysis and debug.
Experience with PCB design tools and reviewing complex, high-speed layouts.

Preferred Qualifications:
Familiarity with high-speed interfaces and SI/PI best practices.
Hands-on experience with lab equipment (oscilloscope, logic analyzer, etc.).
Strong knowledge of digital, analog, and power circuit design.
Proven experience leading or mentoring engineers.
Strong problem-solving and decision-making skills.
Clear communication and documentation skills.
Ability to manage multiple tasks and meet aggressive schedules.
Proactive, accountable, and team-oriented mindset.
Experience supporting manufacturing, test, and working with suppliers.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8546365
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Caesarea
Job Type: Full Time
We are seeking a HW Board Design Engineer.

Youll collaborate with top industry engineers within our fast-growing group worldwide.
You will be part of a team driving our groundbreaking next-generation network devices. Our team operates in a startup-like atmosphere within a stable and leading corporation.
Our design center is unique, hosting all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry and building a new internet for the 5G era, with a unified, programmable silicon architecture that will be the foundation of all our future routing products.
Our devices are designed to be adaptable across service providers and web-scale markets, crafted for both fixed and modular platforms. They deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility. We are a transformative technology set to serve our customers and end-users for decades to come.

Your Impact:
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with cross-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.
Requirements:
Minimum Qualifications:
B.Sc. in Electrical Engineering from a leading academic institution.
4 years of experience as a board design engineer, with a strong background in executing complex hardware projects.
Experience in high-speed designs and multi-layer PCB design.
Hardware-oriented, with experience in lab work (measurements/characterization, lab equipment).
Hands-on experience in PCB bring-up and debugging.

Preferred Qualifications:
Demonstrated success in leading multi-disciplinary projects.
Strong project management abilities, self-driven, with excellent interpersonal skills.
System orientation with a multi-disciplinary approach and multitasking capabilities.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8546522
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דיווח על תוכן לא הולם או מפלה
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שליחה
סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Hod Hasharon and Haifa
Job Type: Full Time
Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.
Requirements:
BSc or higher degree in Computer Science/Engineering or related discipline from a leading university. (alternatively, exceptional proven track record in similar tasks)
5+ years experience in one or more of following disciplines : definition of CPU Architectural features, HW/SW co-design (or SW defined HW), Low level performance profiling and optimization of SW with exposure to CPU ISA, Architecture verification, definition of HW/SW security technologies
Fluent spoken and written English
Behavioral skills: Team player. Although this is not for a manger position, we require interpersonal skills needed to lead partners and colleagues towards achieving a technical goal.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8550298
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