לוח משרות דרושים, לחיפוש זה נמצאו 501 משרות

Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
Responsibilities:
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

As member of the DV CAD team, you have the opportunity to impact our engineers who develop next generation of our products!
You will be responsible for developing software solutions used by thousands of DV engineers globally. You will be supporting design process of all chip families we make (iPhone, iPad, Mac, our Watch and more), and your work will help streamline this complex process. This role combines DV knowledge alongside modern software engineering practices. Your work will be very diverse, and you will have broad impact contributing to the success of us.


You will develop and drive software development of multiple tools across the DV space, including cloud-native services, GUI, LLM harness, CI/CD. Your work will span from software development and architecture to collaborating with DV engineers, working with EDA vendors, and supporting critical project milestones.

Responsibilities
Developing and maintaining LLM harness for agentic DV workflows, and being responsible for benchmarking and improving accuracy of agentic workflows.
Building and managing cloud-native services running on k8s, including CI/CD, containerization, alerting, databases, GUI and monitoring.
Communication with DV stakeholders and working to understand user requirements.
Writing and maintaining Python scripts used as part of design simulation flows.
Supporting multiple projects simultaneously.

As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team.

This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.


Key Responsibilities

Guided Implementation & Learning
Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS).
Assist in macro-level implementation and develop hands-on skills in complex layout routing.
Participate in deep-submicron process challenges under close professional mentorship.

Signoff & Design Integrity Support
Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR).
Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness.
Gain exposure to the rigorous flows required to ensure first-pass silicon success.

Scripting & Cross-Functional Collaboration
Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment.
Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect.
Actively participate in team reviews and technical discussions to ramp up backend methodologies.

As a member of our ML group, you will design, prototype, and ship agentic GenAI systems used by chip design engineers to accelerate their day-to-day workflows. We are looking for a machine learning engineer who is energized by taking LLMs from "promising demo" to "depended-on tool": designing the agent loops, retrieval pipelines, and evaluation frameworks that make this transition real. Success in this role means agents that meaningfully shift how our customer teams work, backed by measurements you trust.

You will join a growing team of ML and software engineers building GenAI solutions for chip design teams. In this role, you will:

Design and build agentic systems featuring multi-agent coordination, long-horizon reasoning, tool use, and planning frameworks.
Develop end-to-end solutions, including domain-specific agents and high-performance retrieval pipelines spanning diverse data sources.
Partner with subject-matter experts on the customer teams to translate their workflows and rules of thumb into concrete agent assignments, prompts, tools, and guidelines.
Build the evaluation backbone for our agents: define success measures, curate offline golden sets, and instrument online telemetry to power feedback loops that drive fast, safe iteration with real cost and quality control.
Drive prompt engineering, model selection, and lightweight model adaptation as the workloads demand.
Collaborate closely with software engineers on the team to productionize your work, and with researchers and customers to shape what we build next.
Stay current with the rapidly evolving agentic and LLM landscape and bring promising techniques into our products with good engineering judgment.

Required SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Required Senior Software Engineer, EDACloud
About the job
Our Cloud's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our Cloud's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. You will anticipate our customer needs and be empowered to act like an owner, take action and innovate. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
The EDACloud team was established to provide tools and support for our rapidly expanding hardware engineering teams. We develop and manage unique software for deploying industry-standard Electronic Design Automation (EDA) tools on Cloud. As a Software Engineer, you will be focused on developing automation, including backend Remote Procedure Call (RPC) services, for seamless tool deployment. Additionally, we're developing cloud-based solutions to scale these workflows effectively, and generate unique insights for our users using advanced machine learning techniques. This critical environment directly impacts hardware creation.
Responsibilities
Design and deploy AI-driven strategies to streamline routine operations and power strategic programs.
Design, implement, and support the transition of custom chip design environments onto standardized, cloud-hosted virtual developer workstations.
Design and implement highly available, distributed services from the ground up, moving beyond automation scripts to robust, production-grade microservices.
Help define the technical roadmap for the teams service stack, evaluating new technologies and cloud-native tools to improve future scalability and performance.
Identify and refactor technical debt within the codebase to improve modularity, maintainability, and code quality.

Our CTO Office AI Research Group is looking for a motivated advanced BSc student to join our team as a Data Preprocessing Engineer. You will play a foundational role in building the data infrastructure that powers our AI research - working directly with large-scale, real-world datasets at the intersection of machine learning and semiconductor chip design.
job requisition id
2604499
This is a hands-on, high-impact student position for someone who enjoys getting into the details of messy data and turning it into clean, structured, and model-ready assets.
What You Can Expect:
Collect, clean, normalize, and sanitize large-scale chip design datasets from diverse sources and formats
Build and maintain scripts and pipelines to automate repetitive data extraction and transformation tasks
Parse and process a wide variety of file formats (JSON, CSV, Parquet, logs, and domain-specific EDA formats)
Navigate complex codebases and directory structures to locate, understand, and extract relevant data
Work with structured and semi-structured data using SQL and Python-based tooling
Collaborate with researchers and engineers to understand data requirements and deliver model-ready datasets
Document data sources, transformation logic, and dataset versions in shared repositories.

This role is for a analog IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.


Specifying requirements and circuit architecture for analog blocks and sub-blocks of an IP, lab bring-up, characterization and debug, write specifications, test plans and characterization reports, work with chip design teams, system HW and SW design teams, ATE PE.

You will be responsible for:
Develop the circuit design of the IPs analog blocks following established design guidelines based on microarchitecture spec. Own all aspects of circuit design development.
Work and collaborate with other designers in the group to deliver results.
Work with FE & BE teams to ensure quality analog integration.
Work with power/performance and functional verification team to define and validate operation sequences.
Work with multi-disciplinary teams to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
Work with post silicon validation groups to ensure the design meets the power/performance targets.

Required Senior CAD Infra Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Work with partner teams to provide the compute, storage, and methodology needs of the chip design, verification, and physical design teams. Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions, and methodologies for ASIC development. Extend the capabilities of third-party tools through their dedicated APIs.
Propose, design, and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow. Lead and actively contribute to the automation and integration of physical design (floorplanning, power planning, synthesis, place and route, clock tree synthesis, timing closure, STA, DRC, LVS, DFM, etc.) in our automated flow.
Leverage your software expertise to develop the hardware automations required for physical design automation, and their software integration in our automated flow.

We are looking for a hands-on engineer to join our Platform Architecture post-silicon team. This team analyzes and tunes the performance and power of Apple Silicon for the Mac, and takes the learnings and measurements to drive SoC architecture change for future chips. If you work comfortably across the hardware/software stack, and the idea to bring up brand-new chips that just arrived from the fab does not scare you but gets you excited, when we would like to hear from you.

You will join a multidisciplinary team of architecture, silicon design, and system software engineers driving the performance and energy efficiency of Apple SoCs. The work spans application software, system software, SoC architecture, and microarchitecture, and sits at the intersection of measured silicon behavior and forward-looking architecture definition. You will build a deep understanding of how current and planned Apple products behave end to end, and use it to influence both hardware and software direction.

Responsibilities
Tune and define SoC memory and fabric performance state controllers on unreleased silicon, and propose improved control and observability mechanisms for future generations.
Plan and execute architecture studies that drive performance and energy-efficiency decisions for future SoCs.
Build tools, workflows, and automation for repeatable analysis of simulated and measured data, including terabyte-scale traces from prototype devices.
Architect hardware features that improve workload characterization and enable robust online control of power and performance.
Debug complex interactions between system software and SoC hardware.
Assess the feasibility of future use cases, SoCs, and products.
Communicate findings across chip design, architecture, software, and system teams to enable data-driven decisions.

As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified

Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices

Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment

We are building the first Neuron performance engineering team in Tel Aviv. As a Machine Learning Performance Engineer, you'll help shape the direction of this team from the ground up - profiling and optimizing workloads across the full ML software stack, writing high-performance kernels, and improving the Neuron SDK that external developers depend on. You'll work at the boundary between software and hardware, collaborating directly with compiler, runtime, and chip design engineers to close performance gaps customers care about.

The team is new and small, which means broad scope, direct ownership, and real influence over the technical direction we take. If you enjoy digging into performance bottlenecks and turning analysis into measurable wins, this role is for you.

Key job responsibilities
Design and implement high-performance compute kernels for ML operations, leveraging the Neuron architecture and programming models.
Profile ML workloads end-to-end to identify bottlenecks - memory, compute, or communication - and drive optimizations through to a measured improvement.
Enhance the programming model and tooling that kernel and model developers rely on, improving usability and debugging workflows.
Identify and drive optimization opportunities across the Neuron software stack (compiler, runtime, frameworks).
Document software designs, operational runbooks, and performance findings so the broader team can build on your work.

A day in the life
You might start your morning reviewing profiling data from a customer's large diffusion model training job, tracing a utilization gap back to a specific kernel. After a design discussion with compiler engineers about a new operator fusion strategy, you spend the afternoon writing and benchmarking a kernel prototype. Later, you review a teammate's pull request for a runtime optimization and share your findings in a short write-up for the broader Neuron organization. Your work directly translates into faster model execution and lower cost for AWS customers running ML workloads at scale.

the company was founded by the team that invented one of the technologies at the heart of 5g. their next vision was to develop an iot sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the iot. this revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.
our investors include softbank, amazon, alibaba, verizon, ntt docomo, qualcomm and pepsico.
we are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. this position involves building and maintaining a complex verification environment, and defining and executing a TEST plan. in this role, you will be leading all aspects of verification and will have a critical impact on the company's r&d path.
responsibilities:
define and implement robust sv/uvm verification solutions, including TEST benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating mix-signals SOC simulation environment using verilog, matlab, hw/sw co-simulation and lab integration.
work closely with digital design, analog design, software, back-end, sw and system teams to understand the functional, power and performance goals of the product and ensure its quality.