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We are looking for an experienced engineer, to help us develop our cutting-edge semiconductor platform.
Youll have the opportunity to join a top-tier, agile, fast-paced team, and take part in the development of the technology that powers the worlds largest cloud provider.
Our Web Services offers a highly reliable, scalable, low-cost cloud platform that enables hundreds of thousands of businesses in 190 countries around the world.
We are looking for talented people to join the Chip Design team in TLV, working on the Nitro product line.
Take an active, significant part in developing the next generations of products that will enable AWS to be the lead in the Cloud sector.

To apply: please compile your CV and university grades sheet into 1 pdf, without both documents, your application cannot be considered.

Key job responsibilities:
Full ownership of one or more IPs within the product:
- Micro-architecture.
- RTL coding and debug.
- Synthesis and timing closure.
- Sign-off.
Supporting the Verification and Emulation teams:
- Test plan.
- Coverage review.
Ensuring that the chip meets quality and reliability standards
Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical issues with innovative micro-architecture and practical logic solutions, and evaluate design options with performance, power, and area in mind.

Responsibilities
Own Networking Internet Protocols (IP's) Design team including definition, implementation and deployment.
Define IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.

What You'll Do:
You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are seeking an experienced Software Engineer to lead the development of cutting-edge solutions aimed to enable CAD design teams to optimize and improve chip design.
In this role, you will collaborate closely with CAD design teams to identify bottlenecks, automate workflows, and simplify dashboard creation, ultimately enabling faster chip development.
Your expertise will be crucial in architecting scalable solutions that empower engineers to efficiently retrieve and search data and enable and optimize ML workflows, including LLM infrastructure of mass impact.
You'll also engage with cross-functional teams to seamlessly integrate the best industry frameworks software solutions, stay updated on industry trends, mentor junior team members, and contribute to the ongoing improvement of software development practices within the organization.
Description
In your role you will architect, design and develop scale-out and distributed solutions to enable better visibility and execution of chip design development.
Role involves debugging and support production environment.
The role also including Interaction with Global CAD teams and design groups across different timezone
This role demands a forward-thinking and integrate best in industry solutions to improve CAD design efficiency
This role also includes building, deploying and supporting complex state of the art LLM infrastructure and ML based systems.

we are looking for a Senior Design Integration Engineer, Google Cloud, Networking
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

we are looking for a Design Integration Engineer, Google Cloud, Networking
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

Will you help us design future generations of revolutionary products? Are you an engineer with a strong foundation and real passion for building new technologies? Do you have track record leading DFT efforts for complex chip designs? Imagine what you could do here. new ideas have a way of becoming excellent products, services, and customer experiences very quickly. Every single day, people do amazing things . Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? You will become part of a hands-on development team that furthers engineering excellence, creativity and innovation.
Dynamic, inspiring people and innovative technologies are the norm here. We want you to join our team if you are an innovative engineer with the dream to research and develop solutions that do not yet exist. In this highly visible role, you will be at the centre of a System-on-Chip design effort. collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
Description
Lead the complete DFT solutions in a chip design by working with chip DFT team to document DFT specifications, and define the SoC test interface Develop and implement DFT architecture Work with the validation team to verify DFT implementations and implement design changes Generate structural test vectors, analyze and improve coverage Work with designers on STA, physical, power and logical issues Work with Test Engineers to bring up test vectors on silicon.

we are looking for a Firmware Engineer, Networking, Google Cloud
Responsibilities
Build C/C++ firmware running on embedded processors with limited memory footprints on the SoCs.
Develop tools to update and debug the firmware, enable emulation, chip bringup, and hardware debugging.
Play key roles in Emulation, chip bring up, and SoC deployment, and contribute to all layers of the data center software stack to deploy SoCs to production.
Create code generators to generate C++ code based on hardware specifications.

You will join our Cisco Silicon One team, the epicenter of Ciscos ASIC design. Our engineers handle every aspect of chip design, from definition and architecture to coding, physical design, and signoff.
Your responsibilities will include:
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with multi-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.

We are seeking a dedicated and skilled team member to assist our customers with integrating DDR/HBM PHY and/or Controller Intellectual Property.
Responsibilities:
In the Applications Engineering team, your main role will be to assist customers with integrating advanced DDR Interfaces into their System On a Chip. These systems are next generation products utilizing our DDR5/4, LPDDR5x/5/4x or HBM3 IP.
The job gives you a chance to work with our IP and the newest industry specifications and applications.
The Application Engineer provides:
Provide technical support and guidance to our customers during their System on Chip (SoC) workflow to address and overcome any technical difficulties.
performs integration reviews at key milestones.
accompany customer's silicon/system bring-up preparation and execution.

we are looking for a Design Verification Engineer, CPU, Google Cloud
As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.

Required SoC Physical Design Engineer, Electrical Analysis
Imagine what you could do here! New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Hardware products. The same passion for innovation that goes into our products also applies to our practices, strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking product! As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC.
Description:
As a member of our physical design team, you will be performing various electrical analyses at the block or chip level, including but not limited to Static/Dynamic IR, EM, Noise, and Signal EM.
You will work with the CAD/technology teams for flow bring-up and validation.
You will also collaborate with the implementation team during the entire chip design cycle to drive sign-off closure for tape-out.
You will handle schedules and support cross-functional engineering efforts.

As a Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full life-cycle of verification which can range from verification planning, test execution or collecting and closing coverage.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

As a Senior CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate with design and verification engineers in projects and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/Universal Verification Methodology (UVM), or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.

We develop high-performance imaging radar for autonomously driving vehicles. The project involves cutting-edge HW, VLSI, mechanics, SW and Algorithms. We are looking for an Experienced Chip Package Design Engineer to be part of our imaging radar HW team.
What will your job look like:
Technical Project lead & Co Design to support the development of IC package with the OSAT, Si, VLSI and System Architecture teams.
Manage co-design meetings with HW, RF and VLSI teams
Design IC packages (e.g., flip-chip, wafer-level, FCBGA) using industry-standard EDA tools (e.g., Cadence APD/SIP, Mentor, Ansys tools)
Manage subcontractors and vendors for development and manufacturing of chip substrate, IC package and IC testing
Simulate high-performance signal/power-integrity chip substrate, including layout, mechanical & thermal simulations
Collaborate and support peer teams from other projects.