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Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team.

This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.


Key Responsibilities

Guided Implementation & Learning
Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS).
Assist in macro-level implementation and develop hands-on skills in complex layout routing.
Participate in deep-submicron process challenges under close professional mentorship.

Signoff & Design Integrity Support
Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR).
Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness.
Gain exposure to the rigorous flows required to ensure first-pass silicon success.

Scripting & Cross-Functional Collaboration
Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment.
Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect.
Actively participate in team reviews and technical discussions to ramp up backend methodologies.

We are looking for exceptional talent to join our team as a Hardware Engineer.
Your Day to Day:
Lead end-to-end hardware development, from architecture and design to testing and production
Design and develop complex electronic systems, including schematics, PCB layout guidance, and component selection
Drive system integration, bring-up, debugging, and validation processes
Collaborate with firmware, software, mechanical, and product teams to ensure seamless system performance
Identify technical risks and propose effective mitigation strategies
Support manufacturing, including design for manufacturability (DFM) and design for testability (DFT)
Analyze and improve system performance, reliability, and cost
Mentor junior engineers and contribute to team knowledge sharing

Semi Conductor Devices (SCD), a worldwide leader of high-end Infrared Detectors and thermal video cores, is seeking a Senior Digital VLSI Engineer to participate in the definition, design, verification, implementation, and silicon validation of next-generation infrared image sensors. Responsibilities • Be part of a team defining future Image Sensor Digital controller Architecture • Participate in the digital design and verification effort of state-of-the-art IR Image Sensors, working closely with the Analog designers and Board designers (internal and external interfaces) • Take part in ASIC development lifecycle (pre- and post-silicon) – from Spec definition to block-level design, full-Chip till Silicon Validation in the laboratory and customer support • Lead the design and integration of complex digital blocks from specification to silicon • Drive VLSI innovation and integration of new technologies into projects and activities in the design organization

Required Edge-AI SOC Verification Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with architecture, software, design, and physical design stakeholders to make technical decisions and represent project status throughout the development process.

Join an agile team working on the most advanced wireless communication solutions, focused on the latest communication standards. You will define the architecture for future products and optimize modem solutions for hardware implementation.
Responsibilities:
Research and define architecture for advanced communication standards.
Define PHY System specifications and architecture for future solutions.
Define low-power architecture.
Work closely with the functional teams (Algorithm, HW/SW, RF, Validation, etc.), from early algorithm study to system validation.
Participate in integration and testing of wireless system solutions, spanning embedded SW, HW and radio.
Support customers engagement and product deployment.

Be part of a dynamic and motivated modem VLSI design team. Take part in a complex SOC VLSI chip-design activities with major focus on advanced digital signal processing and modem subsystem development, covering architectural, front-end design, verification and physical-design aspects.
VLSI development of digital modules from concept to final implementation, meeting physical design entry requirements
Be part of a multi-team developing advanced signal processing cores and subsystem solution
In charge of adjusting, deploying and integrating the subsystem into company design environment.

We are looking for best-in-class STA (Static Timing analysis) Physical Design Engineers to join our outstanding Networking DFT team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:
DFT STA execution, from rtl driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
Be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
Be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part in flows development.

Required Senior SoC Product Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
Drive interactions with wafer fab and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including Return Merchandise Authorization (RMA) support.
Collaborate with cross functional teams across the globe including ATE and SLT Test Engineering, Quality and Reliability (Q&R), Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. Our IC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for our products.

What you'll be doing:

As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.

Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.

Optimize package pin out incorporating system level trade-offs of pins assignment.

Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.

In close co-operation with the SI/PI/HW design teams and product teams.

Planning, ensuring stakeholder management and leading projects from start to finish.

we are a leading company specializing in the development and manufacturing of autonomous drone systems. Its solutions combine hardware, software, and AI-driven technologies to support complex, large-scale operations. our company works primarily with defense industries, such as military and law enforcement agencies worldwide. The company is part of Ondas Holdings and operates as a wholly owned subsidiary.
In this role, you will be part of the electronics engineering team responsible for leading projects end-to-end, including electronics design, drafting, design verification testing, collaboration with internal departments, external suppliers, and supporting development and production phases
Responsibilities
Planning, executing, and documenting verification & validation (V&V) tests for electronic circuits, assemblies, and multidisciplinary systems
Performing functional, electrical, environmental, and integration tests for airborne and ground electronic systems
Preparing, executing, and documenting ATP (Acceptance Test Procedure) and validation test documents
Operating laboratory equipment such as oscilloscopes, spectrum analyzers, signal generators, power supplies, multimeters, and data acquisition systems
Performing hands-on debugging and troubleshooting of electronic boards, communication interfaces, cables, and system-level failures
Supporting integration, bring-up, and verification activities throughout development and production stages
Writing detailed test reports, validation summaries, failure analyses, and technical documentation
Working closely with hardware, firmware, system engineering, integration, manufacturing, and production teams
Supporting qualification, acceptance, and reliability testing processes מול customers, subcontractors, and internal teams
Managing laboratory activities, maintaining test setups, and supporting calibration and organization of lab equipment
Solving technical and system-level challenges under tight schedules and multidisciplinary constraints.

We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA.

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development.

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).

- Verify IO sub-system features, including interconnect protocols and various accelerator engines.

- Develop and debug C embedded SW as part of hardware-software integration verification.

- Build and maintain UVM-based verification environments for various clusters and sub-systems.

- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.

- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).

- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.

- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.

We are seeking a Communication PHY Algorithms Engineer.
This role is focused on the end-to-end research, design, and implementation of digital receivers for proprietary drone communication signals.
Responsibilities:
Mathematically characterize complex communication and signal detection problems. Analyze and assess design trade-offs based on both performance metrics and implementation complexity.
Develop and maintain simulations using MATLAB and Python.
Design digital receiver modules to be implemented either by FPGA of SW.
Implement features directly in SW or technically lead and verify the FPGA implementation efforts of the FPGA engineer.

As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration