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We are seeking a seasoned Sr Staff Physical Design Engineer to provide technical leadership across full-chip and multi-die physical implementation on advanced TSMC FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

What You'll Do
Architect and own the full-chip physical design strategy: floorplanning, power delivery network (PDN), clock architecture, PnR, and timing closure
Define and drive backend methodology standards across the team for advanced node tapeouts (N5/N4P/N3)
Lead critical timing closure efforts - MCMM, OCV, advanced ECO strategies, and cross-corner sign-off
Oversee and guide signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs
Architect and lead the development of scalable PD flow infrastructure using Python and TCL - including automated regression, sign-off reporting, and run management systems
Champion the adoption of Agentic AI in the design flow - define use cases, evaluate tools, prototype autonomous agents for floorplan exploration, timing closure, and ECO automation
Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams
Interface with TSMC, EDA vendors (Synopsys, Cadence, Siemens), and internal research teams to evaluate and adopt new methodologies
Mentor and technically guide junior and mid-level PD engineers across the organization

Required HW Engineer
Job Description Summary
Activities contributing to the design and development of products, solutions and systems. Includes activities linked to technical improvement of existing products and components Impacts departmental operations and responsible for planning/execution. The role has some autonomy but is focused on execution of activities within an operating discipline covered by standard functional practices and procedures. Some judgment may be required but this is typically with guidance.
Job Description
Roles and Responsibilities:
Hands on developing of digital logic (FPGAs and CPLDs).
Analytic discipline approach for FPGA research and development phases, including simulations and verification.
Knowledge with full development cycle of FPGA design.

We are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product
Responsibilities:
Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip.

We are a top global leader, manufacturing smart energy solutions. The company's broad range of products encompasses intelligent inverter and Storage systems, revolutionary EV charger, and by doing that, we are changing the way electricity is being produced and consumed around the world. In this position, We looking for talented Hardware Engineer with R&D Experienced who ready to change the job title to FA Engineer in Q&R. you will be involved in various aspects of the electronic design. As we put a high value on providing best in class product quality and reliability, you will play a critical role in the success of the overall organization. You will be responsible for conducting failure analysis during manufacturing process or service period, determine the root causes and define corrective actions to prevent future occurrences and make sure we are producing best products worldwide. In this position, you will bring deep theoretical background and multidisciplinary understanding.
What you will be doing:
* Performing design review for our different products from the system and architecture level through implementation in design and layout.
* Lead failure analysis processes for company's products. Determine root cause for failures under investigation and implement corrective actions.
* Support Electrical failure analysis process in production and train technicians
 
Country:
Israel
City:
Herzliya

Required SOC Quality and Reliability Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the SoCs that power these data centers by driving quality and reliability processes from the integrated circuit perspective. You will create silicon and follow it into the field (and back) to drive improvements for the next generations of chips.
You will have an understanding of IC flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. Within the larger organization you will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive the strategic definition and development of design-for-reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge/latch-up (ESD/LU), biased highly accelerated stress test (b/HAST), etc.) and conduct failure analysis to resolve quality issues.
Extract and analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical Quality and Reliability models (e.g., ELF, time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) to predict device failure mechanisms and lifetime behaviors.

Required Senior Staff DSP Design Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the architect for high-speed data paths, you will define the roadmap for scaling interconnect speeds. You will evaluate and select key technologies such as Co-Packaged Optics (CPO), advanced modulation formats, and new Forward Error Correction (FEC) methods to support future Artificial Intelligence (AI) computing clusters.
Responsibilities
Identify the "limits of physics" for current Digital Signal Processing (DSP) architectures and pivot the team toward next-generation solutions, such as Machine Learning (ML)-based equalization or optical-specific DSP.
Define the requirements for DSP test chips to validate new architectures in advanced nodes before they hit production.
Drive the long-term power-reduction roadmap, ensuring our interconnects do not become the thermal bottleneck.
Represent us in the Optical Internetworking Forum (OIF) and Institute of Electrical and Electronics Engineers (IEEE) standards, ensuring our hyperscale requirements for latency and power are reflected in global specifications.

Required SOC Quality and Reliability Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the-art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. You will have an opportunity to create silicon and follow it into the field and back to drive improvements for the next-generations of chips.
You will have an understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis is expected. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. You will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.The AI and Infrastructure team is redefining whats possible.
Responsibilities
Lead the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Establish and direct the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge and latch-up (ESD/LU), and biased highly accelerated stress test (b/HAST)) and conduct in-depth failure analysis to resolve quality issues.
Analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical quality and reliability models (e.g., early life failure (ELF), time-dependent dielectric breakdown (TDDB), or negative bias temperature instability (NBTI)) to predict device failure mechanisms and lifetime behaviors.

Required Silicon Generalist III
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Haifa, Israel; Tel Aviv, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Define, develop, and execute post-silicon validation test plans on both pre-silicon emulation setups and physical silicon platforms in the lab.
Lead the bring-up of silicon, troubleshooting and identifying root causes of complex hardware and software issues.
Work closely with Architects, Design Engineers, Firmware/Software developers, and production teams to drive bug fixes and ensure feature functionality.
Provide comprehensive functional coverage for our custom designs, driving the transition from a prototype chip to a fully realized product deployed globally.

As a Pre-Silicon Verification Engineer, you'll work at the heart of chip development, collaborating across teams to ensure our semiconductor platforms meet the highest standards before they reach production.
IO verification team will expose you to the most advanced technologies , as we lead the market with our leaving devices - youll soon have to expertise most advance protocols.

In this role, you'll engage in pre-silicon verification work that connects every phase of our product development journey- from initial product definition through firmware and software development.
You'll collaborate with hardware designers, software engineers, and cross-functional teams to validate complex semiconductor architectures and protocols.
Your days might include developing and executing verification test plans, analyzing simulation results, troubleshooting design issues, and participating in design reviews.
You'll work with advanced verification methodologies and tools, gaining exposure to cutting-edge technologies that define the next generation of cloud infrastructure.

Key job responsibilities
Develop and execute comprehensive verification plans and test cases using industry-standard methodologies and tools.
Design and implement verification environments and testbenches to validate hardware functionality and performance.
Collaborate with hardware design and software teams to identify, analyze, and resolve design issues and verification gaps.
Analyze simulation results and coverage metrics to ensure thorough validation of semiconductor designs.
Contribute to the continuous improvement of verification processes, tools, and methodologies.

Dustphotonics, now part of Credo, is developing cutting-edge technology in Silicon Photonics, revolutionizing connectivity and communication in Data Centers. Silicon photonics is becoming a standard technology used for high performance systems, solving challenges of performance, integration, power and cost. This technology is growing rapidly also in other markets such as Healthcare, LIDARs and other sensors. We are looking to solve the difficult problems, in a smart and simple way, by thinking out of the box, leveraging the knowledge and know-how of the team members and work as team to create Magic. We believe in working hard but having fun on the way to success. We welcome you to join our team - Apply for your next career opportunity with us! We are seeking a talented and motivated R&D Physicist with strong hands-on experience in optical laboratory work, photonics testing and physics-based data analysis. In this role, you will be responsible for designing and carrying out experiments for SiPh chip performance and characterization, performing and analyzing laboratory experiments of chip-level optical systems assembly, and developing test setups for photonics and laser device characterization. The ideal candidate combines strong experimental skills with the ability to analyze complex physical data, develop Python-based analysis tools, automate workflows and translate measurement results into clear technical insights for the R&D team. This role may require international travel for demonstrations, exhibitions and technical activities as needed.


Responsibilities:



* Design and carry out experiments for SiPh chip performance and characterization.
* Perform and analyze laboratory experiments of chip-level optical systems assembly.
* Develop, manage, and improve setups for photonics and laser device characterization.
* Analyze optical, electrical, and electro-optical measurement data using physics-based models and statistical methods.
* Develop Python-based tools, scripts, and Jupyter notebooks for data analysis, visualization, automation, and reporting.
* Build algorithms for test data processing, performance extraction, trend analysis, and failure/root-cause investigation.
* Support automation of lab equipment, data acquisition, and test flows.
* Apply DOE, statistical analysis, and modeling techniques to improve testing methodologies and product understanding.
* Work with R&D, design, test, and engineering teams to translate experimental results into actionable conclusions.
* Contribute to the development of new testing methodologies, data-analysis methods, and characterization techniques.
* Maintain clear documentation of experiments, analysis flows, code, and results.
* Ensure adherence to experimental protocols and safety procedures.
* Maintain laboratory equipment and supplies.

Required Staff Design Engineer, Networking, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Haifa, Israel; Tel Aviv, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Required ASIC Design & Verification Engineer
Meet the Team
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab.

​If you are looking to make an impact, come and join a team developing the next generation of space communication technology.
Our mission is to revolutionize the way satellites, space robots and spacecrafts communicate through deep space, in earth orbit and with ground stations. Our technology is based on space proven state-of-the-art proprietary architecture that enables a different approach to the way space communication systems are designed.
We are looking for experienced FPGA Engineers to lead innovation in the next generation space connectivity technology.
What you will be doing​:
Design and manufacture systems including ICs by RS and SoC type FPGAs
Design and implement high-speed digital signal processing algorithms.
Design for highly robust, distributed systems with emphasis on managing physical effects that originate from the harsh space environment.
Implement DSP algorithm on SoC type FPGAs.
Key contributor to Digital, Modem architecture and design.
Lead technical reviews with key stakeholders.
Work closely within a multi-disciplinary team to lead high-impact technical decisions about system design, implementation, and verification.

Required Senior AI SoC Design Verification Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are seeking an experienced Staff/ Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.
This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.
This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.
Key Responsibilities
Define and drive system and chip-level architecture for high-speed connectivity products
Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems
Analyze system requirements and translate them into scalable and efficient hardware architectures
Drive tradeoff analysis across performance, power, latency, area, and cost
Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering
Define and review micro-architecture specifications and ensure alignment across teams
Contribute to standard-based and custom protocols for next-generation AI infrastructure
Support performance modeling, simulation, and architectural validation
Work closely with customers and partners to understand emerging use cases and requirements
Mentor engineers and help build strong technical leadership within the Israel R&D center.