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We are looking for a Hardware Engineer/ Senior Hardware Engineer II (Multiple Roles) - Azure Core.
Responsibilities
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture. 
Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM. 
Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality. 
Interact with software developers and system-validation platforms, as part of the verification/validation flow.  
Oversee and train junior engineers and take leadership roles on large projects. 
Occasional on-call responsibilities for resolving customer issues in production.

our companys Product Engineering group is looking for an experienced Electronics/System engineer to serve as a Technical Project Leader (TPL), join our organization, and be a part of the System Product Engineering organization. The team delivers brand new, high-quality products to our company's customers, applying the following: Development and deployment of automatic testers for our companys network business units (Computing network adapters and High-speed switch systems) including hardware, software, and mechanics; Coordinating and leading all aspects of the analysis of manufacturing data to identify and mitigate quality issues using advanced data analysis techniques such as machine learning, statistical tools, and AI; Leading smooth production and capacity enlargement and failure analysis of return material from customers to understand the reason for failures ;Validating test performance and stability using QA (V&V - validation and verification) methods; The TPL leads projects from requirement until end of life; Engineering manager for SPE projects and technical authority across SPE teams
What youll be doing:
Building integration plans, communicating status and priority among the teams (in/outside of SPE), assessing risks and developing mitigation plans
Leading the project lifecycle in the SPE group, which starts at the requirements stage, through chip design and FW stages till SPE MP, including quality and yields improvement plans
Responsible for bugs management prioritization and tracking and relevant knowledge transfer to the SPE group
Working closely with development teams for environment improvements, such as automation, and driving mitigations to reduce risks
Collaborating with PM for schedule tracking and modifications
Evaluating new technologies and testing capabilities for improvement
Working with the testing architecture team (DFT) to assure testing setups and coverage are met
Engaging with a variety of teams: R&D, HW and SW, Chip design, Operations, thermal, signal integrity, FW and SW, layout, and more, Report project status for high level management.

We are looking for an HW electrical engineer to join our Failure Analysis engineering team under the System Product Engineering group in the company. You will work in a multidisciplinary environment with customers, contract manufacturers, and vendors. This job allows you to work in sophisticated, high-end technology with state of the art products, exciting engineering environment and having a great impact on top technology products, mass production processes, quality and reliability of the company networking products.
What you'll be doing:
Root Cause Analysis and Test Planning: You will perform in-depth root cause analysis by meticulously analyzing failure modes and devising comprehensive test plans. Your expertise in planning and executing tests will be instrumental in pinpointing the underlying causes of failures.
Big-Data-Driven Analysis: Utilizing cutting-edge big-data tools, you will correlate customer-reported failures with production data and RMA history. This data-driven approach will enable you to gain valuable insights into root causes, identify potential risks, and assess the overall exposure of quality issues.
Leading Cross-Organizational Task Forces: You will be responsible for managing and leading cross-functional teams to address quality events and failure modes in our company's networking products. This involves coordinating efforts from various departments, such as hardware, software, and manufacturing, to collectively work towards identifying and resolving issues.
Customer Communication: As a pivotal point of contact, you will proactively communicate with our company's customers to relay RMA root cause findings. Your effective communication skills will help build strong customer relationships and instill confidence in our company's commitment to product quality.
Product Improvement Initiatives: You will play a critical role in enhancing the design, manufacturing process, and testing flow of our networking products. Through analysis processes, you will identify areas for improvement and recommend corrective and preventive actions to address quality complaints.
Hands-on Lab Work: Your expertise will extend to conducting extensive lab work, encompassing hardware, firmware, and software components. This will involve debugging and characterizing system-level, board-level, and chip-level issues, ensuring a robust understanding of product performance.
Continuous Learning and Innovation: Staying updated on the latest industry trends and technological advancements will be essential in fostering innovation and driving continuous improvement within our company's failure analysis processes.

We are looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.

Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.

Power estimation and power modeling.

Which department will you join? The SOC verification group owns the important and challenging job of verifying our company's chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You will manage a team of 5 engineers
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

Which department will you join? The SOC verification group owns the important and challenging job of verifying our company's chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You will manage a team of 5 engineers
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Build C/C++ firmware running on embedded processors with limited memory footprints on the SoCs.
Develop tools to update and debug the firmware, enable emulation, chip bringup, and hardware debugging.
Play key roles in emulation, chip bring up, and SoC deployment, and contribute to all layers of the data center software stack to deploy SoCs to production.
Create code generators to generate C++ code based on hardware specifications.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

The company Networking Advanced Development Software team develops new groundbreaking technologies to enable new market shares for the company and tighten customer relationships. These are emerging technologies in networking and distributed computing for the booming AI factories and data centers. They span areas such as AI neural networks, Deep Learning, High Performance Computing (HPC), Storage, Cloud, SW Defined Network, Network Function Virtualization, 5G NR and more. We develop the solutions top-down, all the way from application behavioral analysis, to architecture definition and down to the implementation, using the world-leading company devices. The development traverses any needed component - application SW, middleware SW, OS kernel subsystems, device drivers, embedded SW (Firmware) and CUDA GPU. We collaborate with partners and key customers in the analysis processes and engage with open source communities introducing our leading features.
What youll be doing:
Design and implement solutions throughout all layers from high level application, OS and driver subsystem to firmware
Work on impactful projects involving state-of-the-art high-performance computing hardware and software
Provide insight and technical guidance and collaborate with peers from across the company - including software architecture, chip architecture, and engineering departments to improve our future technology
Collaborate with our company partners and customers.

we are looking for a Senior Hardware Engineer to join our AV Platform HW Development group in Israel to design the next generation of autonomous driving systems.
What will your job look like?
Responsible for specifying the hardware for our autonomous driving systems
Lead the HW design process: product specification, electrical schematics, component selection, layout, hands-on testing in a lab environment, verification, accompanying production and qualification processes
Define Signal integrity simulations (LPDDR4, MIPI, FPD-link, etc.), perform power integrity (DC drop, PDN AC analysis) and analog simulations (like spice).
Manage the technical interface with our customers to derive the product hardware requirements
Work in collaboration with all the project disciplines: system architecture, mechanical and thermal, software (networking and algorithms), safety and reliability.

we are looking for a Senior Hardware Engineer to join our AV Platform HW Development group in Israel to design the next generation of autonomous driving systems.
What will your job look like?
Responsible for specifying the hardware for our autonomous driving systems
Lead the HW design process: product specification, electrical schematics, component selection, layout, hands-on testing in a lab environment, verification, accompanying production and qualification processes
Define Signal integrity simulations (LPDDR4, MIPI, FPD-link, etc.), perform power integrity (DC drop, PDN AC analysis) and analog simulations (like spice).
Manage the technical interface with our customers to derive the product hardware requirements
Work in collaboration with all the project disciplines: system architecture, mechanical and thermal, software (networking and algorithms), safety and reliability.

We're looking for a passionate Junior Firmware Engineer to join our PCIe Firmware team.

You will be part of a team whose mission is to develop cutting-edge technology for our network adapters, building the core of the next generation of our devices. In a company at the epicenter of the AI revolution, you will use the most advanced tools to build the foundational hardware that powers it. This is a chance to have a direct impact on our technology by solving sophisticated technical challenges and ensuring our customers can build the future of super-computing and AI fabrics.

What You'll Be Doing:
Design & Develop: Play a key role in the design, development, testing, and optimization of firmware for next-generation network adapters.
Collaborate Across Teams: Partner with world-class chip design, verification, software, and architecture engineers to define and craft new low-level firmware flows.
Solve Complex Problems: Investigate, debug, and resolve challenging firmware issues, contributing to robust, long-term solutions.
Drive Innovation: Help improve our team's methodologies and automated processes, contributing to our knowledge base and making everyone more effective.

Join our GPU Hardware Verification team in Raanana, Israel, and help shape the future of the worlds most widely deployed GPU architecture Mali. As a Principal Verification Lead Engineer, youll guide the technical direction for complex GPU verification programs, mentor talented engineers, and influence methodologies that set the standard for our next-generation graphics processors. Your work will make a visible impact across multiple projects, ensuring that our technology continues to deliver outstanding performance and quality for millions of users worldwide.

What Youll Do:
Define and lead verification strategies for sophisticated GPU systems.
Shape and evolve verification methods and frameworks to improve coverage, scalability, and efficiency.
Anticipate challenges and design practical, forward-thinking solutions that help multiple teams succeed.
Lead the Technical Vision:
Take full ownership of end-to-end verificationplanning, execution, and deliveryfor advanced GPU components and subsystems.
Apply advanced techniques such as coverage-driven, random, and formal verification.
Be responsible for verification reviews, sign-offs, and integration of block-level and system-level environments.
Collaborate and Influence
Act as the primary technical contact across Architecture, Design, and Product teams.
Coach and mentor engineers, helping them grow their skills and confidence.
Chip in to continuous improvement in our verification tools, flows, and CI systems.
Innovate with Purpose:
Bring creativity and technical excellence to how we verify hardware.
Drive automation and efficiency through scripting and next-generation verification tools.
Represent our leadership in verification internally and externally.

we are a global leader in autonomous driving technologies and advanced driver-assistance systems (ADAS). Our cutting-edge solutions, including the EyeQ chip, our company SuperVision, our company Drive, and our company Chauffeur, leverage computer vision and machine learning to enhance vehicle safety and enable self-driving capabilities. Integrated into millions of vehicles worldwide, our technology is redefining the automotive industry and driving the evolution towards smarter, safer, and more autonomous mobility. We are seeking a skilled and driven Algorithm Team Lead to research, develop, and deploy state-of-the-art lidar based techniques that deliver world-class results, enabling the safe development of Autonomous Driving features and Advanced Driver Assistance Systems. ** This position requires on-site presence at our Jerusalem office one day per week.
What will your job look like:
As an Algorithm Team Lead, you will guide a team of talented developers to:
Design, develop, and implement lidar based algorithms in both C++ and python to solve complex problems
Collaborate with cross-functional teams to understand requirements and deliver robust solutions
Conduct research, evaluate existing models and techniques, and propose innovative approaches to improve algorithm performance and accuracy
Optimize existing algorithms for better performance and scalability.

The EyeQ SoC Performance Modeling and Profiling team is part of the EyeQ Platform Group (EPG), working on both current and next-generation designs for ADAS (Advanced Driver-Assistance Systems) and Autonomous Vehicles (AV). Performance models and profiling tools are essential components of the EPG infrastructure they are used during the hardware architecture definition phase of the EyeQ chip and by software developers to optimize performance.
What will your job look like:
You will be part of team that develops EyeQ SoC Performance Modeling environment and emulators
You will work on SOC performance analysis and optimizations.
You will be running HW benchmarks, to measure HW performance and to calibrate the simulation environment to match the performance of the silicon board.
You will be working on HW performance analysis and tuning, and influence future company EyeQ SoC design.
You will have the opportunity to work on open-source simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/Algorithms developers.