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Required Senior Hardware Test Engineer
Description
The Senior Hardware Test Engineer is responsible for developing, implementing, and sustaining test processes and equipment used in the manufacturing of hardware products. This role ensures that products meet quality, reliability, and performance standards through robust test strategies, automation, and continuous improvement. The engineer acts as a bridge between design engineering, manufacturing operations, and quality assurance, supporting new product introductions (NPI) through to mass production and sustaining phases.
This is a great opportunity to be part of one of the fastest-growing AI infrastructure companies in history, an organization that is in the center of the hurricane being created by the revolution in artificial intelligence.
Role and Responsibilities:
Test Development & Validation:
Design, develop, and implement test plans, test fixtures and infrastructure.
Collaborate with R&D to define test requirements early in the product lifecycle.
Develop test scripts and automation software (Python, LabVIEW, C#, etc.) to improve coverage and efficiency.
Validate test coverage, yield, and reliability through statistical analysis (GR&R, Cpk, SPC).
New Product Introduction (NPI):
Support EVT, DVT, and PVT phases with test readiness and execution.
Lead test process transfer to contract manufacturers (CMs) or ODM partners.
Train CM engineers/technicians on test systems and procedures.
Ensure compliance with safety, regulatory, and customer requirements.
Manufacturing Support & Continuous Improvement:
Monitor production test yields, debug failures, and drive root cause analysis (RCA).
Implement corrective actions and continuous improvements to reduce test time, cost, and false failures.
Maintain and calibrate test equipment and fixtures.
Support ECO (Engineering Change Orders) by updating test plans and equipment accordingly.
Cross-Functional Collaboration:
Work closely with hardware, firmware, and reliability engineers to improve product testability and robustness.
Partner with Quality and Operations to ensure smooth scaling into mass production.
Engage with suppliers and CM partners on test strategy alignment.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.

We are looking for an excellent Firmware Design Engineer for NVIDIA FW PHY Group. The person will closely work with NVIDIA FW development, architecture, chip design teams and gain deep understanding of NVIDIA's Networking products and technologies.

What youll be doing:

Enabling new SerDes and Optical Technologies.

Implement FW functionality in signal processing units of our products.

Work closely with the architecture, HW, and SW design teams.

Define implement and maintain FW algorithm to control the Silicon.

Develop and test FW on emulation & simulation environments during the Pre-silicon phase.

Debug and screen HW/FW/SW issues.

Take an active part in silicon bring-up and SW development phases.

Lead data-driven discussions about the product functionality and areas for improvement.

we are seeking an experienced power integrity/presi reliability engineer. as part of our team, you will be working with multiple projects across several teams worldwide. developing tools, flows and methodologies and their deployment in the projects, working on cutting edge technologies in the scope of the power integrity and reliability.
what you'll be doing:
working on implementing and developing tools and flows covering ir-drop and electromigration.
adapting and designing flows and methodologies to custom project needs.
ensuring robust power integrity and reliability.
perform power integrity analysis and mitigation.
collaborate with other design teams on power delivery strategies.

we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are seeking a Senior or Principal Backend Engineer for our Tel Aviv R&D center to join the Talon team, which is responsible for our Enterprise Browser. In this role, you will be instrumental in developing a key security solution that protects businesses by isolating web sessions, preventing data leaks, and managing security policies. You will take a leading position within the team, owning and leading feature development from end-to-end and delivering substantial improvements across the entire product to enhance our multi-layered security approach.
Key Responsibilities
Design, implement, test, and deploy significant features for the Enterprise Browser backend services, contributing to all phases of the development lifecycle.
Take full ownership of specific feature segments, demonstrating accountability for quality and timely delivery from conception to release.
Proactively collaborate and exchange information with cross-functional teams to ensure seamless integration of product features and infrastructure.
Drive innovation by contributing ideas and participating in brainstorming sessions to challenge our approach and enhance product capabilities.
Simplify complex technical problems and focus on the details to deliver high-quality, robust, and performant solutions.
Actively share knowledge and mentor other engineers, contributing to a positive and collaborative team dynamic that empowers others.
Continuously seek opportunities for improvement within team processes and the product itself by applying learnings and challenging the status quo curiously and positively.

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.


Key Responsibilities


Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
Own the design database structure and version control to ensure team alignment and data integrity
Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

Take part in developing the worlds leading ecosystem-security solution
Address security, scalability, and performance challenges
Work closely with other team members, provide technical leadership
End-to-end ownership of features, from design through development and deployment
Take part in uncovering and resolving critical vulnerabilities for some of the biggest companies out there

DRS RADA is a global pioneer in radar systems for active military protection, counter-drone applications, critical infrastructure protection, and border surveillance. We are seeking a Junior Automatic Test Equipment (ATE) Software Engineer for an on-site position at our manufacturing facility in Beit She'an. As a Junior ATE Software Engineer, you will take part in the development and maintenance of advanced ATE software for electronic cards and calibration systems used in our cutting-edge Active Electronically Scanned Array (AESA) radar technology. You will collaborate closely with a multidisciplinary team to ensure the functionality, accuracy, and performance of our ATE systems. Key Responsibilities: ATE Software Development: Participate in the design, development, testing, and maintenance of software for Automatic Test Equipment used in electronic card)PCBA( testing and AESA radar calibration. Integration: Work collaboratively with hardware/system engineers to integrate ATE software with testing equipment and devices, ensuring seamless operation. Debugging and Troubleshooting: Support identification and resolution of software issues, system failures, and compatibility problems. Documentation: Maintain accurate and up-to-date technical documentation. Quality Assurance: Support quality control activities to ensure that ATE software meets project requirements. Team Collaboration: Work closely with cross-functional teams, including hardware engineers, software developers, and project managers. Continuous Learning: Stay up to date with industry trends and emerging technologies and contribute to the improvement of ATE software and testing methodologies.