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We are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

Our group is looking for a talented student to join us in developing the next-generation state-of-the-art switch & GPU products. Working with the Industry leaders in Data Centers, High-Performance Computing, Storage Platforms and more.

What you will be doing:

Work in a combined design and verification team which develops some of the Formal Verification core units.

Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to performance.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

With the growing demand for traffic bandwidth in datacenters, efficient physical high-speed communication becomes a crucial part of the development of silicon ASCs that serve networking infrastructures. We are looking for a PHY (Physical Layer) Architect for our Architecture team. We are positioning you to a key role to face this challenge and become part of our team, so we can continue developing the best devices in the industry.

Our networking architecture group is seeking for a highly skilled, leading engineer to explore, and define the Physical layer of our products. As a lead engineer, you'll be responsible to define and drive features and have responsibility on the Physical layer architecture. The role will include definition of both the hardware circuitry and the firmware/software that is involved in operating the physical layer communication, with emphasis on the former. We are searching for hardworking, enthusiastic, engineer which has both highly technical skills as well as good personal skills, in order to be able to lead cross groups activities.

What you will be doing:

Lead projects across team, starting from processing requirements and definitions from customers and translating those into detailed technical specification for hardware architecture, system embedded software, user interface and high-level design.

Supervise the implementation of projects by team-leaders / developers / QA, participate in low level design reviews, QA test plans reviews, and keep track of changes and handle obstacles.

Define the architecture of implementing physical layer standards into our ASIC devices.

Involved in standard bodies activities and definition of next generation protocols.

Define features for the phy layer, to exploit interoperability between different generations of communication.

Be involved in product definition and the high-speed protocols that the company`s networking devices will support.

Work closely with multi-functional teams - design, backend, system, marketing, firmware, driver, etc. Provide architecture definitions and as a result converge on key design decisions.

Become focal point for our physical layer networking communication devices.

We are looking for an excellent Firmware Optics Verification Manager to join the Optical FW group. As the team manager, you will be leading a major development team responsible for the next-generation optical modules products while being hands-on with development activities. The verification team develops cutting-edge networking features for 1600GbE Data Centers and Networks of tomorrow. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced. Are you ready for the challenge?


What you will be doing:

As a Optic Firmware Verification Manager, you will lead a group of firmware verification engineers, using your expertise in C++ and Python in an Agile methodology to drive the verification strategy.

Manage the verification process, aligning with quality standards and project timelines.

Drive and facilitate the planning, scheduling, and execution of the project and activities of the team

Collaborate with architecture and different software design teams as part of the software development lifecycle.

Work in pre and post-silicon development environments of next-generation our Optics modules products.

Gain a deep understanding of networking technology, system debugging and stacks, as well as the HW/FW/SW relationship.

Innovate! Bring our FW Optics products to shine in customers view

We are now looking for Chip-Design student for the Switch Silicon group.

As a chip design student in our Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units specializing in quality of service.

Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

We are now looking for chip-design and verification student for the Switch Silicon group.

As a chip design student in our company Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units specializing in quality of service.
Build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to power, area, and performance.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are looking to hire a deeply technical, creative, and hands-on advanced-development researcher to prototype and evaluate novel networking technologies for our Ethernet datacenter solutions, focusing on distributed AI training, High-Performance Computing, Cloud, Storage, network programmability, end-to-end network software stacks, and SDN. We are a world leader in high-performance computing technology, AI, and networking with ambitious plans for future systems. This position offers the opportunity to have a real impact in a research-focused team in a dynamic company. The networking advanced-development group is chartered to research and incubate new technologies that will re-define the future data centers and supercomputer performance and functionality. Advanced development software researchers represent us in open-source projects, conferences, and standard bodies.

What you'll be doing:

Developing proof-of-concept implementations of new technologies, and thereafter guiding their incorporation in company products.

Evaluation and analyzing new technologies at scale.

Optimizing collective communications and distributed AI training, and HPC communications. Improving performance on our supercomputers, researching distributed solutions for next-gen data centers networking.

Software development and architecture, ranging from application behavioral analysis and algorithms, network simulations, middleware, and API design, down to implementing OS subsystems, device drivers, FW, and HW modeling.

Customer engagements, academic research collaborations, publishing white papers, blogs, RFCs, and conference lectures/BOFs.

We are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Work in a combined design and verification team.

Design and verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area, and performance.

Daily work involves all aspects of chip development: Design, Micro- Architecture, Firmware, Production, and Verification.

We are looking for a Senior Chip Design Verification Engineer for developing the next generation DFT technologies.

As a Senior Chip Design Verification Engineer in the DFT team in our coompany, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.
As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

This is a highly visible position in CSG (Switching Group). We are looking for DFT engineer that wants to be part of the best implementation team, that performs a true RTL to production.
The DFT position involves ownership of testability, methodology and execution for assigned projects. The DFT engineer is responsible from RTL DFT insertion to final test program bring-up. The DFT engineers are implementing Boundary scan, MBIST, SCAN and SCAN compression, and more. They are generating all patterns and work on the chips final test programs.

Required DFT/Synthesis Design Engineer
Responsible for writing timing constraints, running synthesis and implementing DFT (including scan, MBIST and IP testing), you will work on our next generation 5G IC and interact with software, signal processing algorithms, integration and layout teams.

Required ASIC Design Engineer
Within the BBIC team, you will be responsible for the specification, design and validation of various modules linked to our next chipsets generation.
You will work closely with our other teams (software, signal processing algorithms and integration).
RESPONSIBILITIES
Micro-architecture definitions at the unit level
Specification, design, RTL coding and optimization of complex blocks
Close work with the verification team on block/top level to ensure timely delivery of quality designs.