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Principal Software Engineer Data Platform ( Cortex)
Job Summary:
Join the Cortex team as a Principal Backend Engineer and own the backend strategy for our integrated detection and response engine. You will be responsible for transforming raw endpoint, network, and cloud data into actionable intelligence, using AI-driven techniques to dramatically reduce false positives and focus our defense on what truly matters: stopping the worlds most critical threats.
Key Responsibilities:
backed by the massive scale and resources of a global leader, to architect and scale a world-class data infrastructure capable of processing billions of events per second in real-time.
Integrate state-of-the-art AI technologies to transform raw telemetry from the industry's leading cyber products into high-fidelity, actionable intelligence.
Own the end-to-end software development life cycle, from conceptualizing complex distributed systems to deploying high-performance code, building AI-augmented systems that are fast, maintainable, and resilient.

We're seeking a BD Team Lead to own and grow our outbound business development function -

building pipeline across Balance's full product suite, including pay-by-invoice and order-to-cash

(O2C).

This role reports directly to the VP of Sales.

Benefits:

Mission-driven culture with a strong focus on personal growth.

Hybrid work model: 3 days per week in our Tel Aviv office.

Stock options.





Responsibilities
Lead and coach a team of BDRs, setting quota, pipeline targets, and day-to-day priorities.

Own outbound strategy and execution across Balance's full product suite.

Partner with Sales and Marketing to keep BDR-sourced pipeline aligned with target segments and ICP.

Report on team pipeline metrics and surface insights that inform BD strategy.

Recruit, ramp, and develop BDRs as the team scales.

Location: Tel Aviv, Berlin, London, or New York This is one global position, which can be based in any of the locations above. We’re looking for the best person for the role and are flexible on location. ?Why Mindspace? At Mindspace, we're redefining what the workplace can be. Founded in 2014, Mindspace has grown into one of the world's leading premium flexible workspace providers, operating nearly 50 locations across Europe, the US, and Israel. More than beautifully designed workspaces, we are a hospitality-driven company built around exceptional service, inspiring environments, and vibrant communities. Our success has been built by ambitious people who care deeply about creating remarkable customer experiences, developing outstanding teams, and constantly raising the bar. As we continue to grow profitably and expand our global footprint, we're looking for leaders who want to shape the future of work- not simply manage it. Based in Tel Aviv, our global headquarters and one of Mindspace's largest and most strategic markets, this role offers a unique opportunity to work alongside our executive leadership team and influence both the Israeli business and the company's global direction. Why This Role? This is Mindspace’s most senior global marketing leadership role, with full ownership of the company’s global Marketing function. As Senior Director Commercial, you will lead the Marketing organization globally and serve as the company’s senior-most marketing leader, reporting directly to the COO. The role sits at the intersection of Marketing, Sales, Revenue Operations, Digital and Member Experience, with Marketing at its core. You will own and strengthen the commercial engine that drives demand and revenue across our markets — from building a powerful global brand and generating high-quality leads, through enabling our sales teams with the right data, tools and processes, to improving conversion across the entire customer journey. We’re looking for a true all-around marketing leader who can connect brand, PR, online and offline marketing, growth and performance into one strong commercial strategy, while leading and developing the global Marketing team. You will also play a key role in shaping our revenue operations, digital customer journey and member experience, working closely with Sales, Operations, Product and our regional leadership teams to build a scalable commercial model across markets. What You’ll Be Responsible For
* Lead Mindspace’s global Marketing function and organization, with full ownership of the company’s marketing strategy, team and performance across brand, PR, growth & performance, digital, field marketing and offline channels.
* Drive high-quality lead generation and full-funnel performance, from acquisition and lead qualification through tour booking, conversion, deal close, renewals and retention.
* Build and strengthen the commercial engine behind our sales organization, including data, dashboards, reporting, lead management, sales enablement materials and processes that help our teams perform better in the field.
* Strengthen Mindspace’s key acquisition channels, including SEM, SEO, brokers, partnerships and other digital and offline lead-generation channels.
* Use data, customer insights, CRM and funnel metrics to improve conversion, attribution, commercial performance and ROI.
* Partner closely with Sales and regional leaders to continuously improve how we generate leads, manage opportunities, conduct tours and convert prospects into customers.
* Own and improve the digital commercial journey, ensuring our website, app and other digital tools strengthen the Mindspace brand while driving engagement, conversion and commerce.
* Help shape the member experience across our physical locations, connecting the brand promise with the offline customer journey, community experience, events and on-site engagement.
* Develop additional revenue opportuniti

We are looking for an exceptional Senior / Principal Backend Engineer to join our AppSec Platform group, reporting directly to the Group Leader.
This is a highly autonomous, hands-on role for an engineer who wants broad technical ownership rather than a narrowly defined domain. You will work on some of AppSec's most important and challenging engineering problems - spanning high-scale distributed systems, data infrastructure, onboarding and integrations, developer experience, reliability, performance, and AI-driven engineering.
You will frequently operate across team boundaries, take ambiguous problems from idea to production, and lead technical initiatives that have an impact well beyond a single service or team.
We are looking for someone who combines deep backend expertise with strong execution: an engineer who can design the architecture, dive into the code, debug production systems, challenge existing assumptions, rapidly prototype new approaches, and bring others along with them.
Key Responsibilities:
Lead Critical Initiatives End-to-End - Own complex, business-critical engineering efforts from problem definition and architecture through implementation and production, often spanning multiple teams and domains.
Build and Scale the Backbone of AppSec - Design and evolve distributed systems and data infrastructure supporting large enterprise environments and hundreds of millions of entities, while balancing scalability, reliability, performance, and cost.
Stay Hands-On and Raise the Engineering Bar - Write and review production code, solve complex technical problems, and champion excellent architecture, maintainable code, testing, observability, and production ownership.
Drive Performance & Reliability - Identify architectural and operational bottlenecks and lead meaningful improvements in scalability, resiliency, efficiency, observability, and production readiness.
Shape DevEx and AI-Driven Engineering - Improve how engineers build, test, debug, and operate software while leveraging AI, automation, and agentic approaches to accelerate development and unlock new capabilities.

As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.


Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments.
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence.
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments.
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners.
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.
Be responsible and go-to person for any IR related issues.

As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified

Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices

Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment

As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities
Execute SoC Top-level physical design and actively drive full-chip convergence.
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff.
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR).
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon.
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration.

As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Staff / Principal ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support.
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions.
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams.

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient.
Apply design techniques to meet PPA (Power, Performance, Area) targets.
Contribute to design quality through verification and validation activities.

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives.
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter.
Collaborate effectively across teams to ensure seamless integration.

As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.

As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Staff DFT Engineer, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy
Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support.
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards.
​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies.

Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production.
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance.
Drive test coverage and quality metrics to meet stringent manufacturing requirements.

Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR.
Participate in developing and maintaining cutting-edge DFT implementation flows.
Automate and improve methodologies using advanced scripting and tools.

As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.

Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.