our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Experienced Physical Design Engineer to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Requirements: BSc or MSc degree in Computer Engineering or Electrical Engineering.
3+ years experience in the Physical Design field.
Experience with high speed interfaces (DDR/PCIE) - an advantage.
Experience with advanced nodes (5nm and below) - an advantage.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
Building or maintaining implementation tools and flow - an advantage.
Experience in scripting languages like Tcl/Python/Perl/TCSH.
This position is open to all candidates.