We are looking for an experienced STA Engineer to join our growing BE team. We are working on the most challenging and interesting ASIC chips. Come join us and have a big impact on our groundbreaking and innovative designs.
Responsibilities:
Take part in STA activities for blocks, Sub Systems and Full chip, from definitions to TO.
Analyze timing results, verify correctness and provide timing budget for the different partitions.
Own the timing constraints both for STA and P&R flow.
Working closely with architecture, design, PD and DFT teams to make sure timing closure and ensures product success.
Identify risks and bottlenecks, work closely with PD, RTL and DFT teams, ensuring convergence throughout various project stages.
Participating in design methodology, reviews and tool automation work and definition.
As part of this rule you will gain very good understanding of our HPC and AI designs and sub system as well as product targets.
Requirements: BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years experience in STA (Prime-Time/Signoff).
Experience Full chip STA on complex SoCs experience.
Expert knowledge and hands-on experience in timing closure & signoff methodologies.
Good knowledge of DFT architecture and DFT timing related issues
Good knowledge of Async timing concepts & verification.
Good knowledge of the full backend flows from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs)
This position is open to all candidates.