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Required Design and Power Methodology Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design and Power Methodology Team Manager within the Server Chip Design team, you will be responsible for managing and leading design and power methodologies from IP to SoC, pre and post silicon. You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
You will work closely with CAD vendors and internal teams to develop lead design and power methodology and execution.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead flow and methodology development and assimilation across multiple groups. Work closely with CAD tool providers as well as internal CAD teams.
Plan, execute, track progress, assure quality, and report status.
Work closely with internal customers and support multiple activities and deliverables.
Drive design methodologies such as design construction, CDC, RDC, SDC. Drive power at: IP and SoC RTL/Gate Level Optimization, estimation, correlation.

Required Senior SoC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Participate in test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Hardware Emulation Technical Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Define the emulation strategy, identify platforms and technologies to support all customers.
Explore emulation methodologies, gather feedback from customers, and implement emulation workflows at scale.
Support emulation customers with debugging hardware, software, tooling, and project-specific issues.
Create tooling and automation to support emulation tools, licensing, and job management in our infrastructure.
Act as a primary interface to emulation vendors.

Required Software Engineer, CPU Performance Modeling, Cloud
About the job
Our software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
In this role, you will work with System teams and the CPU Architecture team to develop an understanding of the Central Processing Unit (CPU), System on a Chip (SoC), performance metrics, benchmarks/measuring tools, and available optimization knobs. You will define methods and technologies to model CPU performance at different accuracy levels by supporting architectural explorations and decision making. You will correlate performance projections with measured post-silicon data.
Responsibilities
Write product or system development code.
Design, develop, test, deploy, maintain, and improve Central Processing Unit (CPU) software modeling and other software tools.
Manage project priorities, deadlines, and deliverables.
Collaborate with hardware and software CPU Architecture teams, SoC performance modeling team, and other Software teams.

Were looking for a seasoned and driven Team Lead to head our NLP & Speech team. In this role, youll lead a high-performing team of researchers and engineers developing state-of-the-art capabilities in real-time transcription, semantic understanding, content generation, and AI-powered editing tools. Leveraging our unique access to vast multimodal datasets and large-scale compute, your team will drive ambitious applied research projects from concept to deployment - powering intelligent, intuitive experiences for millions of content creators.

Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Cloud customers, and billions of users worldwide.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.) and Cloud. Our end users are Googlers, Cloud customers and the billions of people who use our services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Required Senior SOC Performance Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Validate performance and power models from the architecture team and lab measurements against established goals, exercise open source benchmarks, analyze the results, and identify optimization opportunities.
Design and build tests to verify SoC design meets targets, and implement advanced technologies for running "benchmark representations" on pre-silicon environments.
Analyze problems to identify core design weaknesses, and drive resolution of performance issues in both pre- and post-silicon environments.
Collaborate closely with design, validation, and architecture teams to ensure hardware and software designs interface correctly and deliver products.
Develop performance measurement frameworks, including Key Performance Indicators (KPIs), to produce regular reports and dashboards that support stakeholder decision-making, and drive efforts to productize features that improve performance and power characteristics.

we are looking for an experienced Product Line Manager (PLM) for the IoT portfolio to lead product-line planning and execution across the full lifecycle of IoT solutions. This role will own roadmap definition, market and customer requirement analysis, product specification, launch readiness, and ongoing business growth for a portfolio that includes IoT gateways, cellular routers, industrial switches, and related services and platforms. The role works cross-functionally with R&D, solution management, business development, sales, marketing, operations, global services, and partners and OEMs to turn IoT value proposition into market wins.
Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.
Responsibilities
Own the IoT product line lifecycle from strategic planning through execution, launch, and lifecycle management.
Define and maintain the portfolio roadmap, balancing short-term customer needs with long-term strategic priorities.
Translate market needs, customer use cases, and competitive input into product requirements, business cases, pricing and COGS targets, and time-to-market plans.
Lead PLM-owned stages in the feature and release lifecycle, including feature requests, high-level business case creation, GTM readiness, and go / no-go decisions.
Define product functionality through technical specifications and use cases, and work closely with R&D to ensure high-quality end-to-end delivery.
Drive commercialization of IoT portfolio, including offers around secure and resilient SCADA transport, smart IoT solutions, and industrial and utility connectivity use cases.
Work with marketing and product marketing on positioning, launches, presentations, data sheets, webinars, GTM toolkits, and sales enablement content.
Partner with sales and account teams to support customer opportunities, RFIs / RFPs, partner discussions, and strategic deals.
Manage and prioritize initiatives tied to IoT differentiation, including security-by-design, certifications, protocol conversion, edge intelligence, and resilient communications.
Monitor market trends, competitor activity, and adjacent technologies such as private LTE / 5G, edge computing, AI / ML integration, and industrial IoT applications to shape roadmap decisions.
Where relevant, manage partners and OEM relationships, including specifications, commercial alignment, customizations, and sales support.

we are looking for a Experienced Verification Team Leader.
Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.
Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station
Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs