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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are , cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
design and build tests to verify that the SOC design meets those goals.
develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre- and post-silicon environments.
develop performance measurement frameworks, including key performance indicators (kpis), to produce regular reports and dashboards that support stakeholder decision-making.
Requirements:
minimum qualifications:
bachelor's degree in Computer Science, computer engineering, or electrical engineering, or equivalent experience.
8 years of experience in SOC or central processing unit (cpu) performance and power modeling, analysis, and debugging.
experience with computer architecture, focusing in the areas like interconnects, traffic quality of service (qos), distributed caches, and i/o flows.
experience in programming languages such as C, C ++, or similar.
experience in identifying, troubleshooting, and solving performance problems.
preferred qualifications:
experience with hardware description languages like verilog or systemverilog.
experience in one or more functional areas, such as coherent fabrics (e.g., amba chi/axi), memory controllers (e.g., lpddr5, ddr5), or i/o controllers (e.g., pcie, cxl).
experience in productizing features that enhance the performance or power characteristics of a design.
experience in building fast, accurate SOC /cpu performance models in C ++.
experience in pre-silicon and post-silicon analysis and debugging.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8592868
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
lead an asic subsystem and understand how it interacts with software and other asic subsystems to implement groundbreaking data center networks.
define high-performance hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
implement designs in systemverilog.
collaborate with software, verification, and physical design stakeholders to ensure the designs are complete and correct.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience architecting networking asics from specification to production.
experience developing rtl for asic subsystems.
experience in micro-architecture, design, verification, logic synthesis, and timing closure.
preferred qualifications:
experience architecting networking switches, end points, and hardware offloads.
experience working with design networking like remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience working with software teams optimizing the hardware/software interface.
experience in tcp, ip, ethernet, pcie, dram, network on chip ( NOC ) principles and protocols.
experience in a procedural programming language (e.g., C ++, Python, go).
understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592849
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
perform register-transfer level (rtl) coding (coding and debug in verilog, systemverilog), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power closure activities.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, rtl design concepts, and languages, such as verilog or systemverilog.
experience with logic synthesis techniques to optimize rtl code, performance and power, as well as low-power design techniques.
experience with design sign-off and quality tools (e.g., lint, cdc, etc.).
experience with SOC or ip architecture.
preferred qualifications:
master's degree or phd in electrical engineering, computer engineering, Computer Science, or a related field.
knowledge of high-performance and low-power design techniques, assertion-based formal verification, field-programmable gate array (fpga) and emulation platforms, and SOC architecture.
knowledge in one of the following areas such as double data rate (ddr)/low power double data rate (lpddr), high-bandwidth memory (hbm).
excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592851
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דיווח על תוכן לא הולם או מפלה
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שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as the design for TEST (dft) engineer lead, you will play a crucial role in dft architecture and dft design, and support devices to production. you will be responsible for providing technical leadership in dft, developing flows, automation, and methodology, planning dft activities, tracking the dft quality throughout the project life-cycle, and providing sign-off dft to tapeout.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
lead and execute dft activities in the design, implementation, and verification solutions for application-specific integrated circuits (asic).
develop dft strategy and architecture, including hierarchical dft, memory built-in self TEST (mbist), and automatic TEST pattern generation (atpg).
work with other engineering teams (e.g., design, verification, physical design) to ensure that dft requirements are met and mutual dependencies are managed.
manage a dft team planning, deliverables, and provide technical mentoring and guidance.
lead dft execution of a silicon project, planning, execution, tracking, quality, and signoff.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, or a related field, or equivalent practical experience.
8 years of experience in design for TEST from dft architecture to post silicon production support.
4 years of experience with people management.
experience with dft design and verification for multiple projects, dft specification, definition, architecture, and insertion.
experience with dft techniques and common industry tools, dft and physical design flows, and dft verification flow.
experience in leading dft activities throughout the whole asic development flow.
preferred qualifications:
master's degree in electrical engineering or a related field.
experience in post-silicon debug, TEST or product engineering.
experience in jtag and ijtag protocols and architectures.
experience in SOC cycles, silicon bring-up, and silicon debug activities.
knowledge of fault modeling techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592844
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
in this role, youll work to shape the future of ai/ml hardware acceleration. you will have an opportunity to drive cutting-edge tpu (tensor processing unit) technology that powers google's most demanding ai/ml applications. youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's tpu. you'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on tpu architecture and its integration within ai/ml-driven systems.
as a design technology co-optimization (dtco) engineer, you will bridge the gap between process technology and product architecture to define the next generation of datacenter-class silicon. you will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures.in this role, you will conduct place and route experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules. you will collaborate with foundry, ip, and architecture teams to identify power, performance, and area (ppa) bottlenecks and drive system technology co-optimization (stco) initiatives.your work will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify ppa gains. by navigating the trade-offs between process complexity and design performance, you will ensure googles hardware achieves efficiency and power density.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
execute high-fidelity place and route experiments to evaluate the ppa impact of advanced process features, library architectures, and design rule variations on datacenter-class ip.
drive design technology co-optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track he
דרישות:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in physical design (rtl-to-gds) or technology development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
experience with industry-standard place and route (p&r) tools and static timing analysis (sta) tools.
experience in cmos device physics, finfet/nanosheet architectures, and the impact of layout parasitics on ppa.
experience in scripting and automation using tcl and Python (or PERL ) to manage design sweeps and data extraction.
preferred qualifications:
master's degree or phd in electrical engineering, computer engineering or Computer Science, with an emphasis on computer architecture.
experience in design technology co-optimization (dtco), including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
experience working with major foundry technology files (pdks) and interpreting design rule manuals (drm) to guide physical im המשרה מיועדת לנשים ולגברים כאחד.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592810
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
we're the driving team behind groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhsic hardware description language (vhdl)), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience architecting networking asics from specification to production or equivalent experience.
experience developing rtl for asic subsystems.
experience in micro-architecture, design, verification, logic synthesis, and timing closure.
preferred qualifications:
experience working with design networking: remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience architecting networking switches, end points, and hardware offloads.
experience working with software teams optimizing the hardware/software interface.
experience in a procedural programming language (e.g., C ++, Python, go).
knowledge of tcp, ip, ethernet, pcie and dram.
familiarity with network on chip ( NOC ) principles and protocols (axi, ace, and chi).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8592780
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סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
22/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Were currently seeking a Senior Developer Technology Engineer, Artificial Intelligence. Would you enjoy researching parallel algorithms to accelerate AI workloads on advanced computer architectures? Do you find it rewarding to identify and eliminate system bottlenecks to achieve the best possible performance on pioneering computer hardware? Could you be thrilled about an opportunity to partner with the developer community, working at the forefront of technology breakthroughs that contribute to the success of an industry leader like us? If so, the Developer Technology Team invites you to consider this role.

What you will be doing:

In this position, you will research and develop techniques to GPU accelerate workloads in deep learning, machine learning or other AI domains.

Work directly with other technical experts in their fields (industry and academia) to perform in-depth analysis and optimization of complex AI and HPC algorithms to ensure optimal AI solutions on modern CPU and GPU architectures.

Publish and/or present discovered optimization techniques in developer blogs or relevant conferences to engage and educate the developer community.

Influence the design of next-generation hardware architectures, software, and programming models in collaboration with research, hardware, system software, libraries, and tools teams.
Requirements:
What we need to see:

An advanced degree in Computer Science, Computer Engineering, or related computationally focused science degree (or equivalent experience).

You have 8+ years of relevant experience in software development or research work.

Programming fluency in C/C++ with a deep understanding of algorithms and software development.

A background that includes parallel programming, e.g., CUDA, OpenACC, OpenMP, MPI, pthreads, etc.

Hands on experience doing low-level performance optimizations.

In-depth expertise with CPU and GPU architecture fundamentals.

Effective communication and organization skills, with a logical approach to problem solving, good time management, and prioritization skills.

Ways to stand out from the crowd:

Expertise in parallelization and performance optimization of Deep Learning models arising from Natural Language Processing, Computer Vision, Recommender Systems, etc.

Excellent understanding of linear algebra.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8586910
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
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שליחה
סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
22/03/2026
Job Type: Full Time
We're looking for a Senior AI/MLOps Engineer to join a group that specializes in Security and Networking, and specifically ML, AI and agent development. As a Senior AI/MLOps Engineer, youll build and maintain the infrastructure, tools and processes necessary to support the AI lifecycle in a production environment. You will collaborate closely with data scientists, software engineers, security architects and DevOps teams to ensure smooth deployment, modeling and optimization of AI models. This role involves creative problem solving alongside engineering teams, and is pivotal for the continued success of AI networking security.

What youll be doing:

Developing, improving and optimizing scalable infrastructure for handling and deploying security and networking AI models and agents in production, ensuring high availability, scalability, reproducibility, and performance.

Optimizing AI models and agents for performance, scalability, and resource utilization, considering factors such as latency, efficiency, and cost.

Monitoring and deploying agentic systems, LLMs, and ML models in production.

Designing and implementing frameworks/pipelines for AI training, inference, and experimentation.

Collaborating closely with data scientists, security architects and software engineers to operationalize and deploy AI models and agents, including packaging and integration with existing systems. Participate in developing and reviewing code, design documents, use case reviews, and test plan reviews.

Collaborating with DevOps teams to integrate pipelines and workflows into the CI/CD process, ensuring flawless deployments and rollbacks.

Building and maintaining monitoring and alerting systems to proactively identify and resolve issues relating to quality, performance and infrastructure.

Implementing access controls, authentication mechanisms, and encryption standards for AI models and data.

Documenting guidelines, and standard operating procedures for MLOps/AI processes and sharing knowledge with the wider team.

Develop proof-of-concepts for new features.
Requirements:
What we need to see:

BSc/MSc in CS/CE or related field (or equivalent experience).

Strong background in AI with experience deploying and monitoring AI/ML models, LLMs and agents to production systems at scale, including distributed and multi-node environments - at least 5 years of experience.

Proficiency in programming languages such as Python, Java, or Scala, along with experience in using ML/AI frameworks and libraries (e.g. TensorFlow, PyTorch).

Proficiency in microservices architecture, container orchestration, cloud platforms, and scalable infrastructure for training and inference workloads.

Knowledge of inference optimization techniques.

Understanding of build infrastructure and CI/CD tools and practices (e.g. GitLab, GitHub Actions, Jenkins).

You are detail-oriented and care deeply about robust, well tested, high-performance code in production environments.

You are proactive, take full ownership of your deliverables, have a can-do approach, and excellent communication and collaboration skills, able to work effectively in multifunctional teams.

Ways to stand out from the crowd:

Knowledge of network protocols and Linux internals.

Security and networking background, with knowledge of security protocols, network architectures, firewalls, intrusion detection systems, and other relevant security and networking concepts.

Experience deploying and optimizing generative models and agents.

Knowledge of network security principles and practices.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8586605
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
22/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Help build an Always-On, low-overhead GPU profiling service that runs in production, scales across cluster environments, and delivers actionable insights for ML workloads. You will be hands-on delivering our profiling solutions across system software, drivers, and CUDA to make profiling continuously available and reliable.

What youll be doing:

Develop low-overhead, high-reliability implementations in C/C++, with bounded CPU/memory budgets.

Lead end-to-end feature delivery spanning user-mode components, driver/platform layers, and performance counter/trace providers.

Establish profiling models that integrate with existing ML/AI workflows (e.g., PyTorch/XLA) to turn low-level signals into actionable insights.
Requirements:
What we need to see:

BS or MS degree or equivalent experience in Computer Engineering, Computer Science, or related degree.

5+ years of system-level C/C++ development, including concurrency, memory management, and performance engineering.

Familiarity with system software design, operating systems fundamentals, computer architectures, performance analysis, and delivering production-quality software.

Strong interpersonal, verbal, and written communication; able to influence across organizations and build trust with external collaborators.

Ways to stand out from the crowd:

Extensive experience with profiling/tracing stacks for CPU/GPU (e.g., CUPTI, Nsight, performance counters, event correlation) and debugging highly concurrent systems.

Deep hands-on knowledge of CUDA and GPU architecture, including runtime/driver APIs, CUDA streams/graphs, and kernel behavior.

Track record building continuous, always-on, or multi-client profiling systems designed for predictable overhead at scale.

Hands-on experience tuning ML training/inference loops based on deep profiling analysis, with familiarity in ML ecosystems (e.g., PyTorch, JAX) and correlating application events with GPU metrics to translate data into actionable performance insights (e.g., bottleneck triage, compute vs. memory bound).

Experience with user-mode driver development and integration within platform security and permissions models.
This position is open to all candidates.
 
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8586600
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22/03/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are now looking for an Arch Simulation Manager to join our Networking team! As a Switch-Arch Simulation Manager in our Networking Business Unit, you will lead a team of highly skilled hardware engineers responsible for verifying the next generation of our cutting-edge Switch products. This is a unique opportunity to make a real impact at the heart of our AI and HPC revolution, while working in a fast-paced, innovative environment. You will be part of a passionate and experienced team using modern approaches to validate the performance requirements for the next generation of our networking products. Your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and storage applications.

What Youll Be Doing:

Lead and grow a team of hardware verification engineers focused on Arch performance validation of complex digital designs.

Collaborate closely with Architecture, Design, DV teams to identify verification needs and drive closure.

Provide technical guidance, mentoring, and support to engineers in the team.

Own the planning and execution of simulation deliverables to ensure high quality and timely tapeouts.
Requirements:
What We Need to See:

BSc or MSc in Electrical/Computer Engineering, or Computer Science.

3+ years of managerial experience in a chip design or verification domain.

8+ overall years of overall industry experience in modeling, hardware verification, or RTL design.

Excellent leadership, problem-solving, and communication skills.

Ways to Stand Out from the Crowd:

Hands-on experience with modeling.

Networking and Switch specifically experience.

Background in developing modeling testbenches, regression environments, and CI/CD workflows

Managerial experience in chip design domain

A passion for recruiting , leading , mentoring engineers and building strong, collaborative teams.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8586547
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
22/03/2026
Location: Tel Aviv-Yafo and Ra'anana
Job Type: Full Time
We are seeking an excellent Firmware Manager to join to GPU networking (NVLink) FW group in Tel-Aviv / Raanana. You will have the opportunity to lead development team responsible for the firmware of the next-generation networking products while being hands-on with development activities. We drive the data growth of the worlds biggest companies. With dedicated engineers around the globe, the work environment is dynamic, exciting, and fast-paced. Are you ready for the challenge?

What you will be doing:

Lead a team of engineers and provide technical guidance to the team of highly skilled engineers. Empower the team members to excel and increase team productivity.

Lead the design and implementation of new features in the core of our GPU Networking firmware.

Drive and facilitate the planning, scheduling, and execution of the project and activities of the team.

Collaborate with architecture and different software design teams as part of the software development lifecycle.

Work in pre and post-silicon development environments of next-generation our GPU networking products.

Gain a deep understanding of networking technology, system debugging, and stacks, as well as the HW/FW/SW relationship.

Innovate! Bring our Networking products to shine in customers view.
Requirements:
What we need to see:

B.Sc. in Computer Science/ Computer Engineering / Electrical Engineering.

2+ years of managerial experience.

6+ overall years of relevant overall professional experience.

Proficient knowledge of C (Real-time).

In-depth understanding of firmware and real-time programming, working closely with HW.

Strong analytical, creative, debugging, and problem-solving skills.

Detail-oriented and comfortable with multitasking in a dynamic environment with shifting priorities and changing requirements.

An excellent teammate with good social skills.

Strong programming skills in Python.

Ways to stand out from the crowd:

Knowledge of network protocols.

Experience with Agile/Scrum.

Background in Linux internals.

Experience in operating systems concepts like memory management, and user-space vs Kernel space.

Practical OOP hands-on design experience (Python / C++).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8586507
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
22/03/2026
Job Type: Full Time
We are now looking for a Senior AI System Security Architect! We are looking for an outstanding technical security architect with system architecture focus to design, validate, and guide implementation of secure architecture of its core products. The candidate is expected to: define problems and deliver highly innovative solutions that lead to significant differentiation in the industry, translate customer needs into architectural, technical & strategic direction, and help to resolve objectives & long-range goals of the security organization. Leaders in this role will help reduce risk, threats, and vulnerabilities in our Data Center products and services.

What youll be doing:

Own the security requirements for our networking systems in a variety of product lines.

Work with technical and senior leadership staff to turn business directives into functional implementations.

Collaborate between multiple business units and development groups to ensure a robust and secure product posture, from design to implementation in multiple system level products.

Provide hands-on security engineering expertise across a wide variety of platforms and services.

Provide strategic and tactical expertise in orchestrating, securing, deploying solutions; and in defining relative architectures.

This role extends across multiple groups and excellent working knowledge in the following areas of expertise is necessary for success:

Designing system security architecture at hyperscale.

Embedded systems security architecture and design.

Deep, low level understanding in Root Of Trust (ROT) technologies.

Networking security protocols and concepts.

Operating systems security and SW security concepts.
Requirements:
What we need to see:

BS / MS / Ph.D. in EE or CS. Ph.D. in CS, EE (related technical field) or equivalent preferred.

5+ years of experience in the security industry, especially in System level products including HW, FW and SW components.

Familiarity with System on Chip (SoC) level design or architecture.

Experience with system level threat modeling, risk management frameworks and risk mitigation techniques.

Experience with compute and networking systems security architecture and engineering.

Excellent communication and interpersonal skills. and a consistent track record of driving architectural solutions across organizations.

Ways to stand out from the crowd:

Proven experience in technical customer-facing roles, presenting and discussing security and system architecture requirements and solutions.

Deep understanding of data centers and cloud infrastructure security solutions.

Demonstrated success in driving security innovation across the industry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8586498
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
22/03/2026
Location: More than one
Job Type: Full Time
We are looking for an excellent Firmware Design Engineer for our FW PHY Group. The person will closely work with our FW PHY development, architecture teams and gain a deep understanding of our Networking products and technologies. If you are an outstanding problem solver who loves a good challenge and looking to expand your horizons, come join us!

What you'll be doing:

Work on developing the next generation PHY layer for the Ethernet Switch and NIC (network adapter) product lines.

Be responsible for designing, developing, and delivering new networking features, debugging real problems of FW PHY flows on customer setups.

Innovate! Bring our products to the next quality level.
Requirements:
What we need to see:

B.Sc. in Computer Science / Computer Engineering / Electrical Engineering or equivalent experience.

2+ years of experience with C/CPP embedded.

Knowledge in Linux.

Phenomenal debug skills.

Creative, motivated and collaborative person.

Ways to stand out from the crowd:

Motivation to learn and constantly improve processes and tools.

Experience with Networking applications and protocols.

Background with Git/Gerrit.

Experience with python.

Knowledge of real-time SW.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8586480
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22/03/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for an excellent Firmware Design Engineer for NVIDIA FW PHY Group. The person will closely work with NVIDIA FW development, architecture, chip design teams and gain deep understanding of NVIDIA's Networking products and technologies.

What youll be doing:

Enabling new SerDes and Optical Technologies.

Implement FW functionality in signal processing units of our products.

Work closely with the architecture, HW, and SW design teams.

Define implement and maintain FW algorithm to control the Silicon.

Develop and test FW on emulation & simulation environments during the Pre-silicon phase.

Debug and screen HW/FW/SW issues.

Take an active part in silicon bring-up and SW development phases.

Lead data-driven discussions about the product functionality and areas for improvement.
Requirements:
What we need to see:

B.Sc. or M.Sc. in Electrical or Computer Engineering.

2+ years of relevant experience.

Proficient programming in C.

Debugging experience and ability to investigate and triage difficult problems in embedded FW.

Good communication skills and the ability to work with people across several countries.

Excellent English verbal and written communication skills.

Ways to stand out from the crowd:

Proficient in Python and MatLab.

Good understanding of SerDes operation.

Experience with developing the physical layer of communication protocols.

Knowledgeable of Hardware/Software Development Process.

Strong collaborative and interpersonal skills, with an ability to successfully guide and influence.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8586453
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
19/03/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
seeking a dynamic and highly motivated Software Senior Manager to lead our BlueField DPU Platform software team. We are looking for a candidate who can excel in a sophisticated, multidisciplinary environment, take ownership, and drive high-quality software development including low-level device initialization, Linux OS drivers and kernel configuration, boards bring-up and system management. This position offers the opportunity to have a real impact on sophisticated, groundbreaking products, delivered by us and developed by our customers, empowering the most advanced data centers in the world. We believe our most valuable asset is our people and seek the very best to lead our outstanding team. This role requires close collaboration with teams across various fields (SW, HW, QA) to elevate our product to the next level.

What you will be doing:

Mentor and expand your engineering team in the planning and execution of initiatives and projects with top quality and timely results.

Coordinate feature design and implementation as well issue resolution, as this is a technical leadership role.

Interact with internal and external partners to understand their use cases and requirements. Collaborate with engineering teams, program and product management across the product roadmap.

Continuously review and identify improvement opportunities in established processes, infrastructure, and practices to ensure the teams are implementing in the most efficient and open manner.

Develop a team of engineers who understand the bigger picture, value collaboration, and can take ownership of and implement designs from beginning to end.

Be familiar with the open-source community process to advance industry-standard programming models and platform support while upstreaming and maintaining software into standard software distributions.
Requirements:
What we need to see:

B.Sc. degree or equivalent experience in Computer Science, Computer Engineering, or Electrical Engineering.

12+ overall years of experience in the software industry with specialization in embedded Linux system software stack and Arm preboot development.

4+ years of experience managing managers or senior engineers.

Proven track record of taking several complex software features or products through the full product life cycle.

Strong understanding of computer system architecture, operating systems principles, HW-SW interactions, and performance analysis/optimizations.

Proficient in C, C++ with the technical depth to guide and mentor the team

Experience balancing multiple projects with conflicting priorities.

Flexibility to work and communicate effectively across different teams and time zones.

Ways to stand out from the crowd:

Demonstrated leadership of engineering teams doing embedded Linux and preboot Arm work.

Experience with ARMv8 microarchitecture, ATF, and/or UEFI software.

Knowledge of secure boot flows and/or trusted computing environments is a strong plus.

A good sense of humor is key. We like to have a positive team environment.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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