לוח משרות דרושים הייטק אבטחת מידע / סייבר בתל אביב יפו

XM Cyber is a global leader in hybrid cloud security. XM Cyber brings a new approach that uses the attacker’s perspective to find and remediate critical attack paths across on-premises and multi-cloud networks. The XMCyber platform enables companies to rapidly prioritize andrespond to cyber risks affecting their business-sensitive systems. About the role: Are you a super-talent Senior Software Engineer with a deep passion for cybersecurity and a profound understanding of AI-driven attack techniques? We are looking for a highly professional and responsible R&D member to join our team. This role is for someone who thrives on technical challenges and is ready to leverage their expertise to identify, analyze, and defend against advanced cyber threat Responsibilities: As a Senior Software Engineer in R&D, you will be a key player in the design, development, and deployment of our cybersecurity platform. Your responsibilities will include:
* Leading the research and implementation of techniques to identify and mitigate AI-related attack methods, such as data manipulation and adversarial attacks on security systems.
* Developing and integrating new security features into our platform to proactively defend against modern cyber threats.
* Collaborating with our team to define technical requirements and architectural solutions for cutting-edge security features.
* Tackling challenging technical problems at the intersection of cybersecurity and low-level systems.

We are seeking a hands-on and pragmatic security leader to oversee our information security program. You will ensure our systems, employees, and data remain secure while aligning risk management with business priorities. Youll lead compliance initiatives, drive security awareness, and embed security into company processes without slowing down innovation.

What you'll be doing:

Own and evolve the companys information security strategy aligned to business objectives.
Lead security operations: incident response, vulnerability management, IAM, and vendor risk assessments.
Ensure compliance with SOC 2, ISO 27001, and other customer/partner security requirements.
Partner with Product & Engineering to integrate security by design.
Manage relationships with security vendors, auditors, and consultants.
Conduct regular employee security training and awareness campaigns.
Report on risks, metrics, and posture to the executive team and board.
Build and mentor a small security function (team or outsourced model).

We are looking for an OCC Monitoring Specialist to join our fast-growing OCC Monitoring team. Reporting to our OCC Monitoring Team Leader, you will be responsible for monitoring the infrastructure, applications, and business aspects of the company. We provide the opportunity to become acquainted with the inner workings of the exciting world of Fintech and online payments. Many of our OCC Monitoring Specialists have been promoted internally and integrated into development, DevOps, and product teams.

This position doesn't include a hybrid mode; it only involves working from the office.
We work in 24/7 shifts: 08:00 to 17:00, 17:00 to 00:00, 00:00 to 08:00, including weekends and holidays.


Responsibilities

Responding to events and various technical problems in real-time
Monitoring and liaising activities of the production environment, maintaining the company's monitoring systems, network, business transactions reports, and data analysis regularly
Tracking the events until problems are resolved, contacting the relevant parties in the organisation as needed
Data analysis and fault investigations

Were looking for a top-notch Threat Detection Researcher to join our team
WHAT YOULL DO

Develop detections and tools to protect customers from cloud threats
Investigate attacks on cloud environments and malware targeting cloud workloads
Hunt and analyze real-world attacks and emerging cloud threats
Collaborate closely with the R&D team to transform research insights into product features
Work with customers in response to requests related to suspicious activity or potential incidents
Create best practices and security policies based on research findings
Deliver external-facing content (blog posts and talks at security conferences) based on security insights and novel research

we are looking for a Security Engineer with experience in threat modeling, TTP identification, and detection engineering. Youll work alongside Software Engineers and Offensive Security Engineers to identify critical assets, assess the top risks, and evaluate potential attacks against our company systems. You will be working across engineering teams to develop detection and response automation leveraging both industry-standard and custom detection and response platforms. Youll generate detection ideas utilizing some of the worlds largest data sets and build on top of hyper-scale data pipelines.
Security Engineer - Surface Coverage, Detection Engineering Responsibilities
Lead cross-functional projects to improve our capabilities to effectively detect and respond to security incidents
Review security architecture of large-scale custom and commercial systems and independently propose logging, detection and prevention controls
Perform TTP-based Threat Modeling for a wide variety of assets including endpoints, mobile, servers, internal services, public & private cloud environments and networking equipment
Perform analysis against logs from a variety of sources (e.g., individual host logs, network traffic logs) to identify potential threats and detection ideas
Build response workflows and actions that auto-resolve false positives and provide context scaling our ability to investigate
Support security incident response in a cross-functional environment and drive incident resolution
Design and implement attack testing automation to validate detection coverage
Build logging pipelines using our custom datasets and infrastructure.

Required Application Security Engineer
The Gist
We are one of the fastest-growing healthtech companies, building the technology that connects every part of the healthcare ecosystem. Were solving one of the toughest problems in healthcare: how to make systems, apps, and data truly interoperable.
Our platform enables real-time collaboration between doctors and innovators, with secure data exchange and workflow integrations that happen directly inside clinical systems. In simple terms: we help healthcare work better. By streamlining workflows and reducing complexity, we help organizations focus on what really matters - delivering better care for patients.
Connect & Canvas
At the heart of our platform is Connect, a connectivity layer that links healthcare applications to patient healthcare management systems providers use in real time. Its designed for scale, reliability, and developer experience, powering millions of data interactions every day.

With our recently launched developer platform, were expanding that capability to innovators everywhere, making it possible to build healthcare applications that plug directly into real-world clinical workflows. Our team leads the way in designing, architecting, and scaling these products, experimenting fast, shipping with impact, and shaping the future of healthcare connectivity.
The Role
The ideal candidate will have a strong background in application security, coupled with expertise in product security, infrastructure management, and DevOps practices.
You should be comfortable wearing multiple hats and thrive in a fast-paced, collaborative environment.
Pioneer new approaches to application security, including leveraging AI for advanced automations and process optimizations.
If you're ready to push the boundaries of application security and contribute to a culture of uncompromising quality, we want you on our team.
Join us in our relentless pursuit of robust security and a continuously hardening application landscape.
What you will do
Conduct internal penetration testing against our applications and APIs.
Design, build, and implement the Secure SDLC process, integrating security into all stages of the software development lifecycle.
Evaluate product design and architecture against security best practices, offering guidance on prioritization and remediation.
Build and automate security testing as part of our CICD pipeline and cloud environments based on automation workflows leveraging AI.
Develop and lead projects, implementing various security tools and technologies, such as: AI agents context-aware, SAST, SCA, vulnerability scanners, and Kubernetes (K8s) security tooling.
Mentor development teams through training and hackathons.
Support security incident response in a cross-functional environment.

We are looking for a highly motivated Security Operations (SecOps) Engineer to join our growing security team. The ideal candidate will bring 34 years of hands-on experience in cybersecurity operations and incident response, with strong expertise in cloud environments. You will play a key role in designing, implementing, and managing security monitoring, detection, and response capabilities that safeguard our organizations assets, data, and customers.


Key Responsibilities
Design and maintain monitoring flows and detection use-cases across SIEM and related systems.
Develop, optimize, and tune security rules, alerts, and dashboards.
Integrate threat intelligence feeds into monitoring tools.
Lead and support security investigations, from triage to remediation.
Coordinate with internal teams and external partners to contain and resolve incidents.
Create and maintain playbooks, runbooks, and IR documentation.
Build and maintain security automation and orchestration workflows to accelerate response.
Ensure compliance with security policies, frameworks, and regulatory requirements (SOC 2, ISO 27001, GDPR, etc.).
Maintain clear documentation of procedures, incidents, and improvements.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our companyusers worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, RTL coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Participate in test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.

We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SOC Performance Technical Lead, you will drive the success of our System-on-Chip (SoC) products. You will be focused on ensuring our SoCs deliver maximum performance, power efficiency, and cost-effectiveness. You will be a multi-disciplinary expert who can bridge the gap between deep learning, advanced algorithms, and hardware/software design to create innovative solutions for current and future product lines.
You will lead and oversee a team, setting the technical direction and making critical decisions on frameworks, methodologies, and tools. You will require a collaborative approach with various teams to ensure alignment with organizational goals.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
Exercise open source benchmarks, analyze the results, and find optimization opportunities.
Develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
Analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre and post-silicon environments.
Develop performance measurement frameworks, including Key Performance Indicators (KPIs), to produce regular reports and dashboards that support stakeholder decision-making.