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Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

we are Huawei's Tel Aviv Research and Innovation Center, where we pioneer next-generation data center technologies. Our Future-Data-Center-Infrastructure group specializes in co-designing hardware and software architectures that accelerate AI workloads, optimize resource utilization, and reduce operational costs.
Working at the intersection of academic research and practical implementation, our team develops cutting-edge solutions for AI infrastructure challenges, with a particular focus on Generative AI and large language models (LLMs). We pride ourselves on fostering an environment where system-level thinking, innovation, and technical excellence drive our success in reshaping the future of data center technology.
Role Overview
As a Senior Gen.AI Infrastructure Engineer in our AI innovation team, you'll play a crucial role in advancing our LLM infrastructure capabilities, focusing on research, implementation and optimization of state-of-the-art solutions for model deployment and serving
What will you be doing?
Explore new directions and seek new opportunities for innovation through academic / industry trends tracking
Design and implement advanced optimization techniques for transformer-based models
Conduct research and stay current with academic developments in LLM optimization
Drive architectural improvements for large-scale model serving systems
Develop and optimize infrastructure components using PyTorch and other frameworks
Implement and optimize model serving solutions using frameworks such as vLLM, TGI, and MindIE
Collaborate with cross-functional teams to improve system architecture and performance.