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We are looking for an outstanding Research Team Lead with deep hands-on expertise in large-scale distributed systems, AI framework infrastructure, and performance optimization on custom accelerators. If you are a visionary technical leader, a skilled communicator, and a team builder who thrives at the frontier of systems and AI research - you're welcome on board.
What Will You Be Doing?
Lead and grow a world-class team of researchers and engineers working on distributed AI infrastructure and systems software
Architect and own the software infrastructure enabling distributed training and inference on Huawei's custom accelerator hardware (e.g., Ascend NPU)
Drive research and development on communication libraries, runtime systems, memory management, and graph execution & synchronization at scale
Optimize end-to-end performance across large-scale clusters, covering both scale-up (multi-device) and scale-out (multi-node) configurations
Design and implement high-performance communication backends and collective operations (AllReduce, AllGather, broadcast) for distributed training workloads
Collaborate cross-functionally with hardware architects, compiler teams, and framework engineers to co-design hardware-software solutions
Publish and present research findings at top international venues (NeurIPS, EuroSys, SC, MLSys, OSDI) and represent the team externally
Mentor engineers and researchers, conduct performance and growth reviews, and shape team culture and technical direction
Partner with top academic institutions and open-source communities to advance the state of the art in distributed AI systems

We are looking for an outstanding Research Team Lead with deep hands-on expertise in large-scale distributed systems, AI framework infrastructure, and performance optimization on custom accelerators. If you are a visionary technical leader, a skilled communicator, and a team builder who thrives at the frontier of systems and AI research - you're welcome on board.
What Will You Be Doing?
Lead and grow a world-class team of researchers and engineers working on distributed AI infrastructure and systems software
Architect and own the software infrastructure enabling distributed training and inference on Huawei's custom accelerator hardware (e.g., Ascend NPU)
Drive research and development on communication libraries, runtime systems, memory management, and graph execution & synchronization at scale
Optimize end-to-end performance across large-scale clusters, covering both scale-up (multi-device) and scale-out (multi-node) configurations
Design and implement high-performance communication backends and collective operations (AllReduce, AllGather, broadcast) for distributed training workloads
Collaborate cross-functionally with hardware architects, compiler teams, and framework engineers to co-design hardware-software solutions
Publish and present research findings at top international venues (NeurIPS, EuroSys, SC, MLSys, OSDI) and represent the team externally
Mentor engineers and researchers, conduct performance and growth reviews, and shape team culture and technical direction
Partner with top academic institutions and open-source communities to advance the state of the art in distributed AI systems

we are looking for a payment specialist to be part of the Finance team in Israel (the company is located in both Hod Hasharon & Haifa, the position is in Hod Hasharon)
As key positions for treasury security department, perform high quality payments and collections, ensure compliance with companys policies and procedures.
Processing payments and funds transfer on different e-banking platform, and ensure there are no errors by conducting the necessary checks;
Manage issues in the payment process, such as bank system problems, payment rejections, refunds, etc. Verify the root causes and resolve them to ensure timely payments.
Assist in the providing of bank statements, identify issues in bank statements and resolve them;
Establishment payment rule book guidance, consider the optimization points in the work, to make daily operations more standardized and control payment risk;
Support and perform necessary cooperation for APs department month closing;
Managing the Expense reports reimbursement for all employees
Assist with other finance tasks as needed, such as managing financial operations, assisting FP&A with preparing budget reports etc.,Qualifications and Professional requirements

We are looking for a highly analytical, detail-oriented Innovation Expert to join our Open Innovation team. This role is ideal for an individual contributor operating at the intersection of deep tech, the startup ecosystem, and academia, with strong technology analytical skills, clear communication, and a foundational background in computer architecture research.
In this role, you will drive our external innovation strategy by managing academic research collaborations, scouting early-stage deep-tech startups, and conducting technical due diligence.
Key Responsibilities:
Academic Cooperation & Research Partnerships: Identify and build direct collaboration agreements with world-class professors, research labs, and universities. Facilitate joint research projects, tech-transfer initiatives, and track academic spin-offs.
Startup Scouting & Ecosystem Mapping: Actively identify, source, and map early-stage deep-tech startups and emerging tech companies globally within the companys strategic domains.
Technical Due Diligence: Evaluate startup technologies, product-market fit, and team capabilities. Analyze technical validity and assess how external innovations align with our internal roadmaps.
Ecosystem Analysis: Conduct deep-dive analyses of startup ecosystems, venture capital trends, and academic spin-offs to identify high-potential investment and collaboration opportunities.
Investment & Collaboration Support: Synthesize technical and commercial findings into clear, structured scouting reports, investment tech memos, and presentations for senior leadership to drive partnership or investment decisions.
Cross-Border Collaboration: Act as a bridge between startup founders, academic innovators, and internal global teams (including European and China-based business units) to facilitate joint POCs, or investment reviews.
Track Tech Domains: AI infrastructure, advanced semiconductors, hardware-software co-design, and AI data movement.

we are looking for a Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system

we are looking for a Computing Network & System Architecture Group Leader.
In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture.
As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.

We are looking for a Senior AI Modeling Architect to define and model the architecture of our next-generation AI processors. In this role, you will serve as a key technical authority - bringing not only strong modeling capabilities, but also the architectural vision to propose and drive end-to-end solutions to complex design challenges.
You will work at high levels of abstraction, partnering closely with HW and SW architects to co-invent optimal solutions, validate them through simulation, and influence design decisions based on experimental data.
Responsibilities:
Model CPU/AI processor functionality and performance using SystemC and pre-silicon simulation environments
Define and drive architectural solutions - not only identify problems, but come with concrete proposals and alternatives
Partner with lead HW and SW architects to co-design features and evaluate trade-offs across the stack
Analyze bottlenecks and performance on workloads reflecting future AI use cases
Provide proof-of-concept implementations for new architectural features and design alternatives
Potentially lead feature definition in addition to the modeling role

we are looking for a Compilation Technology Expert.
This team will operate under a unique manner, as described below -
The environment
- Startup-like intensity
Small team
High ownership
High visibility
Merit is the essence, not titles
- Fast pace
Todays state of the art is tomorrows baseline
We aim to go beyond
- Incubator mindset
Take on hard challenges, dismantle, and regroup as novelty
- Elite technical culture
Strong experts
Strong standards
Strong execution.
Ratio beats seniority, not the other way around
- No artificial boundaries
We challenge assumptions, and question constraints, and leave no quarter
- Direct exposure to the latest and greatest AI technology
Real hardware
Real toolchains
Real large-scale AI applications
All pass through and impacted by our work
- First-principles thinking
out-of-the-box is a compromise
Do not accept that a box had to exist in the first place.

We are seeking an experienced C++ Developer with a strong background in building sophisticated systems to join our innovation group. This role focuses on developing a Browser Detection and Response (BDR) System aimed at enhancing browser security for users worldwide.
Key Responsibilities:
Design, develop, and maintain new complex C++ features with an emphasis on chromium browser security and internals.
Collaborate with teams across the world for productization
Contribute to the innovation and enhancement of security features within browser technologies.
Why Join Us:
Work on projects impacting billions of users.
Collaborative and innovative environment.
Competitive salary and benefits.

we are looking for a HW Architect team leader.
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing:
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence

we are looking for a Senior HW architect.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

Research and Innovation Center, is looking for an experienced software engineer with expertise in Linux kernel and virtualization design + development to join our Future-Computing-Infrastructure expert group. The group designs and develops technologies for the next-generation data center aimed at accelerating AI workloads for a unique HW, optimizing compute resource utilization and reducing data-center costs. Our projects involve hardware and software architecture co-design. They require high-level system understanding, creativity and innovative thinking.
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!
What will you be doing?
Design and develop Linux kernel code related to virtual memory management and memory-tiering
Research, design and innovate methods, algorithms and supporting data-structures for managing memory hierarchies in virtualization environments
Participate in research to analyze AI-based applications performance, identify bottlenecks and optimize various decision-making mechanisms based on benchmarking results
Collaborate with professional team members and various global teams around the world on a daily basis
Challenged to think outside of the box and come up with creative ideas to deal with complex challenges within Linux kernel

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

we are looking for a Senior Core Power Management Architect.
Job Description:
Will drive the implementation of autonomous core power management for best performance and power efficacy.
The Power expert will take charge in understanding business-units (customers) needs, and translate them to CPU core solution.
This expert will utilize his power management experience to deliver world-class power efficient HW-SW solutions for Huawei products.
Responsibilities:
Responsible for bringing Huawei CPU to a leading position in Performance-Power efficiency.