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At Infinidat, a Lenovo company, we empower enterprises and service providers with cutting-edge storage platforms that redefine performance, reliability, and cyber resilience at scale. We are looking for a Tech Lead to join our System Validation & Verification team - someone who combines deep hands-on automation expertise with the leadership skills to drive technical direction, mentor engineers, and own end-to-end quality strategy for a complex, enterprise-grade distributed storage system. This role is centered on test design and development - the ideal candidate is someone whose craft is writing and owning tests for complex product features, and elevating a team to do the same at a high level. If you thrive at the intersection of architecture, code, and quality - and get energized by the challenge of making large-scale systems provably correct - this role is for you.

Responsibilities:

* Lead the technical direction of the automation group: define best practices, set coding standards, and guide architectural decisions for testing methodologies and new feature implementations
* Remain hands-on: actively write, review, and contribute to test code alongside the team, leading by example rather than by title
* Design detailed test plans for new features, and review and approve implementation designs proposed by team members for how those features will be tested
* Engage with R&D and Product from the earliest stages of feature development, providing input on testability, edge cases, and quality requirements before implementation begins
* Design and own test strategies for large, cross-cutting features involving multiple services and components working together
* Mentor and grow team members, conducting code reviews and elevating the team's engineering quality
* Work closely with development, product, and architecture teams to influence design decisions from a quality and testability standpoint
* Drive root cause investigations of complex, hard-to-reproduce issues - race conditions, timing-sensitive failures, and problems that only surface at scale
* Own release sign-off decisions - you'll have the authority to say "not good enough"
* Identify gaps in test coverage across service boundaries and drive initiatives to close them

Imagine what you could do here. , new ideas have a way of becoming extraordinary products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - strengthening our dedication to leave the world better than we found it. Do you want to join us to help deliver the next groundbreaking Apple products?

As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and run-set development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also, you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.
Responsibilities
Develop, improve and maintain all aspects of physical verification flow and methodology
Coordinate the effort of validating flows, improving for custom checks and data generation
Work with the design and PD teams to facilitate the chip design process
Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Collaborate with tool vendors and foundries for PDK performance enhancements

We are looking for a software engineer with strong backend skills, a product mindset, and the curiosity to bring LLM-powered agents into the toolchains and Linux environments where chips are actually designed. Success in this role means owning the agentic infrastructure end-to-end: from the platform our agents run on, to the integrations that let them safely act inside our customers' existing flows.
Description
You will join a growing team of ML and software engineers building GenAI solutions for chip design teams. In this role, you will:

* Architect, build, and operate the agentic infrastructure our team relies on:including LLM orchestration, tool-calling layers, multi-agent workflows, and the services that host them.
* Design and implement software solutions for chip design engineers, translating their workflows into reliable, automated agent-driven systems.
* Integrate our agents and services with existing Linux-based environments, in-house tools developed by the team, and third-party EDA tools.
* Manage agentic and ML workflows in production to ensure performance, high availability, and resource efficiency.
* Deploy and maintain production services, with proactive monitoring to catch quality and infrastructure regressions before they reach users.
* Build automated evaluation frameworks to measure retrieval quality, agent execution, and LLM output accuracy across releases.
* Partner with CAD teams to integrate pipelines and agents into CI/CD, ensuring reliable deployments and safe rollbacks.
* Implement access controls, authentication, and secret-handling practices appropriate for working with sensitive design data.
* Collaborate closely with ML engineers, researchers, and our customer teams.

As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms, enabling early system integration and hardware validation. You will work closely with SoC architects, RTL designers, and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes, methods, and tools for emulation environment development and debug of large complex SoCs.
If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us!
Description
Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
System-level debug and root cause analysis of complex hardware issues on the emulation platform.
IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
Performance profiling and optimization of emulation models to maximize execution speed.
Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
Responsibilities
Own and maintain Palladium emulation build flows for SoC and subsystem-level models
Drive debug and triage of emulation model issues, working with RTL designers and verification engineers
Support system-level hardware validation efforts and hardware integration
Develop reusable debug methodologies and collateral to accelerate issue resolution
Optimize emulation model performance through compile tuning, partitioning strategies, and platform configuration
Thoroughly document flows, debug procedures, and best practices
Collaborate with cross-functional teams to define emulation requirements and support prototype hardware validation