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in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and verification closure. you will verify digital designs, collaborate with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner cases and expose all types of bugs. you will manage the full lifecycle of verification which can range from verification planning, TEST execution, or collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog or formally verify designs with strategic value add (sva) and industry-leading formal tools.
identify and write all types of coverage measures for stimulus and corner cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer pcbs (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (hbm/ddr5).
design and validate high-speed interfaces including pcie gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering >1000a currents with fast transient response for ai processors.
work with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board by debugging hardware issues using oscilloscopes, tdrs, and logic analyzers to root-cause failures to component, assembly, or design issues.

We are looking for a Verification Team Leader for our team in Haifa to drive verification for next-generation PHY IPs . The PHY DV team operates at the intersection of verification, research, and innovation, continuously improving techniques, models, and flows to increase the efficiency and quality of PHY verification. This is a hands-on technical leadership role, combining deep verification expertise with team leadership and close collaboration with design, architecture, firmware, and system teams.
Description
Lead the verification team, including hiring, planning, and communication with management.
Strong teamwork and communication skills.
Responsibilities
Lead the verification team, including hiring, planning, and communication with management.
Define verification architecture and lead for execution
Own verification methodologies, standards, and best practices across the team

we are looking for a Emulation Engineer.
Key Responsibilities:
Set up and maintain emulation hardware infrastructure
Port RTL designs into emulation platform
Debug hardware and software issues
Develop workflows for emulation
Collaborate with emulator vendor FAs
Support users and debug issues

Were growing and looking for a hands-on CAD Engineer who loves building tools that engineers actually enjoy using.
If you like moving fast, owning features end-to-end, and collaborating with smart people across disciplines-come build with us.
Responsibilities
Partnering with multiple engineering disciplines to define, improve, and maintain CAD/EDA development methodologies
Building CAD desktop applications that support EDA solutions and real design workflows
Writing production-quality code, plus unit tests that keep things solid as we scale
The team's vibe:
We value innovation, teamwork, and ownership
Youll have real impact, real autonomy, and a team that actually ships.

We are redefining urban mobility by proving that autonomous vehicles can navigate complex environments using vision-only technology.
As our Hardware Systems Integration Engineer, you will be the lead architect responsible for the "nervous system " of our vehicles. You won't just be selecting components; you will be evaluating infrastructure that enables our AI software to see, process, and React to the world in Real-Time.
Responsibilities:
* Vision-Centric Architecture: Lead the selection and integration of high-dynamic-range (HDR) automotive-grade cameras.
* Compute Platform Selection - Evaluate and benchmark high-performance edge platforms (e.g., NVIDIA Orin, Qualcomm Snapdragon, Ambarella, or custom SOC solutions) capable of handling massive parallel video streams with minimal latency.
* Thermal & Power Integrity: Design integration of computing HW into automotive grade environment. This work can be done with external suppliers.
*  system Synchronization: design and ensure sensor synchronization.
* Redundancy Planning: architect fail-operational hardware systems to ensure the vehicle remains safe even if a specific component or communication bus fails.
* Present to and consult with the group leaders as to hardware design trade-offs