דרושים » חומרה » Senior Core Power Management Architect

we are looking for a Senior CPU Core Architect.
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

we are looking for a HW Architect team leader.
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing:
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence

we are looking for a Senior HW architect.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

We are seeking talented, creative and disciplined engineers to join the best-in-class team that plays a significant part in the development of new silicon for our eco-systems by engaging in a dynamic, highly collaborative environment. As a Wireless MAC System Architect, you will be a core member of our highly innovative and visible Wireless System-on-Chip (SoC) design team that defines modem architectures, develops MAC-layer algorithms, and invents embedded DSP algorithms for chips enabling exciting new wireless applications. You will be responsible for developing state-of-the-art wireless SoC products that are enjoyed by millions of our customers. Application areas include ultra-wideband sensing and specialized wireless audio; products enabled or improved by our teams SoCs include specialized audio headsets (such as AirPods), watches and iPhones.

In this role you will be responsible for the architecture of the Connectivity IP with focus on the MAC sub-system: - Define, document and Spec Connectivity MAC architecture and performance requirements.
- Analyze & simulate the performance of the Connectivity IP in real-life use-cases, achieving benchmarking performances in several metrics, including Throughput, Robustness, Co-existence with other Wireless IPs and more.
- Working closely with other architects (PHY, Power Management, FW and SW) to introduce best in class Connectivity IP solution.
- Develop innovative system architectures and protocols to deliver best-in-class performance for the MAC subsystem of custom wireless silicon solutions.
- Introduce cross-domain features where opportunities exist for innovation to achieve enhanced performance.
- Produce MAC architecture, specifications and corresponding performance/reference modeling in support of digital HW and FW design and verification efforts.
- Develop and maintain a MAC systems infrastructure applying the best methodologies for system-level simulation, pre-silicon prototyping (including emulation and FPGA prototyping), FW QA, regression and MTBF testing, and system verification to ensure first-time design success.
- Support the delivery of new wireless technologies to the Product Systems teams.

We are looking for a Senior AI Modeling Architect to define and model the architecture of our next-generation AI processors. In this role, you will serve as a key technical authority - bringing not only strong modeling capabilities, but also the architectural vision to propose and drive end-to-end solutions to complex design challenges.
You will work at high levels of abstraction, partnering closely with HW and SW architects to co-invent optimal solutions, validate them through simulation, and influence design decisions based on experimental data.
Responsibilities:
Model CPU/AI processor functionality and performance using SystemC and pre-silicon simulation environments
Define and drive architectural solutions - not only identify problems, but come with concrete proposals and alternatives
Partner with lead HW and SW architects to co-design features and evaluate trade-offs across the stack
Analyze bottlenecks and performance on workloads reflecting future AI use cases
Provide proof-of-concept implementations for new architectural features and design alternatives
Potentially lead feature definition in addition to the modeling role

We are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.

We are seeking an exceptional an exceptional leader to build and lead our next-generation internal Analog IP design team. This is a unique opportunity to create a world-class analog design center from the ground up, developing the critical IP blocks that power all of our custom silicon products, including Graviton (server CPUs) and Nitro (networking/security accelerators).

Key job responsibilities
Build the team: Recruit, hire, and develop a world-class analog/mixed-signal design team from the ground up. Define the org structure, roles, and growth path.

Define the IP strategy: Own the analog IP roadmap across all Annapurna Labs products. Evaluate build vs. buy decisions and drive internal capability development.

Drive execution: Lead the full design cycle from architecture through silicon validation - spec, schematic, layout, simulation, tapeout, and bring-up.

Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog IP seamlessly.

Set technical direction: Define design methodologies, flows, and best practices. Evaluate and select EDA tools, PDKs, and foundry processes.

Innovate at scale: Develop IP that is reusable, portable across process nodes, and designed to meet the performance, power, and area (PPA) needs of multiple products simultaneously.

Engage with leadership: Communicate strategy, progress, and risk to senior leadership. Influence the overall silicon roadmap with analog capabilities and constraints.

We are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities:
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

Required Senior System Engineer
Job Description Summary
As a Senior System Engineer, you will play a critical role in the design, development, integration, and verification of complex medical imaging systems. You will be responsible for translating clinical needs into technical requirements, ensuring the robust performance, safety, and regulatory compliance of our innovative healthcare solutions.
Job Responsibilities
Lead and participate in the full product lifecycle, from concept and requirements definition through design, development, testing, and deployment of medical imaging systems.
Translate high-level clinical and user requirements into detailed system and subsystem specifications, ensuring traceability and comprehensive coverage.
Perform complex system analysis, modeling, and simulation to optimize system performance, identify potential risks, and propose innovative solutions.
Collaborate closely with cross-functional teams including hardware, software, clinical, quality assurance, regulatory, and manufacturing engineers to ensure seamless integration and successful product delivery.
Define and execute system verification and validation plans, including test protocols, data analysis, and reporting, to ensure compliance with medical device regulations (e.g., FDA, CE).
Conduct root cause analysis for system-level issues, propose effective corrective actions, and drive their implementation.
Contribute to the continuous improvement of system engineering processes, tools, and methodologies within the organization.
Mentor junior engineers and provide technical guidance on complex system engineering challenges.
Stay abreast of industry trends, emerging technologies, and regulatory changes relevant to medical imaging systems.

We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match - powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
- Micro-architecture definition.
- RTL coding and debug.
- Synthesis and timing closure.
- Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.