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our company seeks a highly motivated senior AI cloud Software architect to join our team in Israel. Work on innovative technologies shaping the future of AI and cloud. We are developing RDMA Transport protocols within the Networking software architecture team at our company. Efficient and fast communication between GPUs directly impacts end-to-end application performance. This impact continues to grow with the increasing scale of next generation systems. This is an outstanding opportunity to advance the state-of-the-art, break performance barriers, and deliver platforms the world has never seen before. Are you ready to build the new and innovative technologies that will help realize our company's vision?
What you'll be doing:
Translate requirements into vision, architecture, and roadmap
Design infrastructure to support programmable improvements to RDMA protocols for E/W AI networking stack
Collaborate with multi-functional teams to innovate and deliver networking solutions
Explore innovative solutions in HW and SW for our next-generation platforms as part of programmable RDMA architecture
Build proofs-of-concept, conduct experiments, and perform quantitative modeling to evaluate and drive new innovations.

we are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer at our company Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

we are looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join Beer-Sheva group, working on RiscV processors platform.
Lead a team of engineers responsible for the functional verification of complex silicon chips, ensuring the designs meet all functional, performance, power, and quality requirements before production. This role involves strategic planning, hands-on technical leadership, cross-team collaboration, and process improvement within the chip development lifecycle.
Define verification methodologies and strategies, ensuring comprehensive coverage of functional, performance, and power requirements.
Plan and manage verification projects, including scheduling, resource allocation, and progress tracking to meet project milestones.

we are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join accelerators IP group in Beer-Sheva/ Tel-Aviv, working on RiscV platform unit and cache coherence IP
design for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance
Daily work might involve any or all aspects of chip development: uarch , Design.
Work closely with Firmware and other groups around the globe.

we are looking for best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you will be doing:
Join accelerators IP group in Beer-Sheva/ Tel-Aviv, working on RiscV platform unit and cache coherence IP
Dynamic verification for chip blocks according to specifications under challenging constraints
Work closely with Firmware and other groups around the globe.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at our company works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the SCAN INSERTION team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
What youll be doing:
You will be in charge of state of the art Design for Test (SCAN INSERTION) flows and implementation
Take full SCAN INSERTION ownership end to end on a project, from Arch & planning to implementation and verification
Inventing and maintaining automation flows that provide SCAN INSERTION implementation to project .

we are looking for best-in-class Physical Design Manager to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Manage and Lead Physical Design team, up to 10 engineers.
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.