As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.
Requirements: Minimum Qualifications:
B.Sc./M.Sc. in Electrical Engineering or a related field.
Hands-on experience with one or more DFT features, such as scan insertion, BIST, or boundary scan.
Proficiency in full product lifecycle development, from pre-silicon design to silicon bring-up and production qualification.
Preferred Qualifications:
Experience with Automatic Test Pattern Generation (ATPG) methodologies.
Strong ability to establish and refine DFT methodologies from design phase to high-volume production.
Ability to quickly learn new concepts and adapt to evolving technologies.
Excellent communication and presentation skills.
Strong attention to detail and system-level understanding of networking and silicon solutions.
This position is open to all candidates.