דרושים » הנדסה » Failure Analysis and Quality Control Team Leader

We are seeking an experienced Team Leader to lead our Failure Analysis engineering group within the Product Engineering team. You will be responsible for controlling and improving the quality of our hardware products through technical leadership, data-driven insights, and global production support. This role requires deep expertise in electronics systems, failure methodologies, production process control, and proven leadership capabilities across multiple geographies.



Key Responsibilities

Lead, mentor, and develop a team of failure analysis engineers while providing technical guidance on complex hardware issues.
Drive continuous improvement of quality KPIs through root cause analysis (RCA), statistical analysis, and yield optimization across all products.
Establish and implement standardized failure analysis methodologies, debug protocols, and quality control processes across global production sites.
Serve as the technical focal point for product design and functionality, supporting the team across RF, embedded, FPGA, high-speed communication, and mixed-signal systems.
Collaborate across Design, Manufacturing, Supply Chain, and Sales teams to resolve critical issues and prevent yield impact.
Manage vendor/supplier escalations and conduct design DFT/DFM (Design for Test/Manufacturability) analyses.
Lead investigation of production crises and manage critical path issues under time pressure.

Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities
Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing.
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration).
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices.
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints.
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance.
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets.
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp.
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews.

Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
Responsibilities:
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Physical Design Lead, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Lead physical design of complex SoC to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the SoC flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
articipate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.

we are looking for an experienced Electronics Engineer to join our growing R&D Hardware team and lead and deliver Hardware projects.
A day in the life and how youll make an impact:
Architect and develop electrical modules from concept through production, including PCB design for new systems and continuous improvement of existing ones.
Bring new components and sensors into product line, working across power supply, communication protocols (I2C, Ethernet, UART), and supporting modules
Serve as the go-to expert for diagnosing and resolving complex electrical faults - you set the standard for root-cause problem-solving.
Partner closely with systems engineers, mechanical engineers, and software teams to shape next-generation features and products from the ground up.
Manage subcontractor relationships for end-to-end module delivery, ensuring quality and timelines stay on track.

We are seeking a highly motivated and experienced Senior System Engineer to join our team and lead the development of sophisticated solutions that push the boundaries of flight.

Responsibilities:

Lead the development of innovative and complex airborne systems.
Develop system requirements that meet customer requirements and product definitions provided by other departments.
Facilitate PMO on developing integration plans identifying timelines, resources and equipment requirements to integrate engineering designs into higher level products.
Define and lead system level test plans to validate that the engineering designs meet requirements.
Collaborate with the R&D and Line of Business managers to ensure timely project delivery.
Define and lead experiments, tests and studies, and/or analytical investigations and provide clear and meaningful results and analysis.
Compile and assist in the presentation of test data collected during design validations to a peer group of engineers.
Work in collaboration with a multi-disciplined engineering team to develop engineering designs/solutions from initial POC to onsite customer implementation.
Contribute to documentation for use in the manufacture, installation, technical support and training related to the final design.
Support engineering products through entire life cycle including assist in installation at customer site, assist in product upgrades and improvements, support of service escalations and product EOL.
Provide regular status of projects to leadership.

Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

We are looking for a hands-on FPGA Design Engineer, specialized in high-performance digital design and FPGA-based system development, as part of the QM-Platform team.

This role involves ownership of FPGA interfaces and connectivity logic, including high-speed communication blocks, platform integration, and close collaboration with embedded and hardware teams. You will work on complex FPGA/SoC platforms, enabling robust and scalable solutions for quantum control systems.

Responsibilities

Own the design and implementation of FPGA-based interfaces such as PCIe, I2C, SPI, and high-speed GT communication.
Develop and integrate FPGA logic on advanced platforms, including Xilinx UltraScale+ and Versal.
Collaborate closely with embedded, hardware, and system teams to ensure seamless HW/SW/FPGA integration.
Drive FPGA bring-up, debugging, and validation at both lab and system levels.
Participate in system architecture definition and cross-team design decisions.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.