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לפני 2 שעות
חברה חסויה
Job Type: Full Time and Hybrid work
A global leader in inspection and metrology solutions for the semiconductor industry, is looking for an experienced HardWare Manager to lead its Hardware Engineering function.
The role combines people management, technical leadership, and ownership of hardware execution across multiple R D projects.
The HardWare Manager will lead experienced engineering teams, define priorities and resources, drive technical decisions, and ensure successful delivery from development through production.
Description
Lead and develop the Hardware Engineering team, including resource allocation, goal setting, recruitment, and professional development.
Own hardware execution across multiple R D projects, driving priorities, schedules, risks, and delivery.
Requirements:
B.Sc. or higher in Electrical / Electronics Engineering or a related field.
10+ years of hardware/electronics engineering experience, including several years in engineering management or technical leadership.
Experience leading multidisciplinary R D teams and taking products from development through production.
Strong understanding of electronic system architecture, analog/digital electronics, power, PCB systems, communication interfaces, sensors, and motion systems.
Good understanding of electrical safety, grounding, EMC, and compliance.
Strong leadership, decision-making, prioritization, and cross-functional communication skills.
This position is open to all candidates.
 
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לפני 3 שעות
חברה חסויה
Location: More than one
Job Type: Full Time
A leading international semiconductors company from the north is looking for an PM system Engineer to lead multidisciplinary development projects in core scanning technologies. This role combines end-to-end project management with strong technical ownership and system engineering responsibility. The ideal candidate will manage complex R D projects from requirements definition through development, validation, and transfer to production, working closely with cross-functional teams to deliver high-quality solutions aligned with company roadmap and customer needs.
Lead and execute multidisciplinary R D projects, from requirements definition through development, NPI, and production readiness.
Own end-to-end project planning, including scope definition, schedules, milestones, deliverables, and risk management.
Requirements:
Bachelors degree in Engineering (Electrical or Mechanical preferred).
At least 3 years of hands-on experience designing and developing multidisciplinary systems.
Experience in Systems Engineering is highly valued, with a solid understanding of system development processes.
Strong knowledge of project management methodologies and proficiency with project management tools.
Proven experience in multidisciplinary R D project management, from project kickoff to delivery - an advantage
Experience in the semiconductor industry - an advantage.
Excellent leadership, communication, and interpersonal skills, with strong attention to detail.
Very good English, written and spoken.
This position is open to all candidates.
 
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חברה חסויה
Location: Haifa
Job Type: Full Time
Our company is seeking a Hardware Development Team Lead to lead cross-functional development and integration activities across the organization. The successful candidate will oversee collaboration between all engineering disciplines, including Hardware, RF, Software, and Firmware, while serving as the key interface with the Systems Engineering team.
Key Responsibilities:
Lead and directly manage a multidisciplinary engineering team developing complex systems, including Mechanical, Hardware, Firmware, and RF engineers, ensuring execution according to project plans, schedules, and objectives.
Lead end-to-end product development, including system architecture definition, technical oversight, prototype development, and design verification and validation (V&V).
Serve as the primary liaison between development engineers, the Systems Engineering team, and Project Managers.
Evaluate, introduce, and implement new development tools, methodologies, and emerging technologies.
Define priorities and allocate engineering tasks based on business needs, project requirements, and market considerations.
Establish engineering methodologies, development processes, project milestones, and required deliverables for internal design reviews (PDR, CDR, etc.).
Define engineering roles and responsibilities, recruit new team members, mentor engineers, conduct performance evaluations, and develop individualized professional growth plans.
Conduct routine management activities, including status meetings, management reviews, and project progress meetings.
Prepare technical responses for project tenders (RFPs), including technical proposals, effort estimation, and cost evaluation.
Provide technical support for both internal engineering challenges and customer-facing technical issues.
Lead internal and customer design reviews as required.
Requirements:
At least 5 years of hands-on experience in hardware development and board design, either as a Hardware Design Engineer or Firmware Engineer.
At least 4 years of experience managing multidisciplinary engineering teams of five or more engineers.
Proven experience leading cross-functional engineering teams.
Demonstrated ability to manage multiple projects simultaneously.
Experience working directly with customers.
Experience preparing technical project cost estimates and pricing - an advantage.
Experience writing comprehensive technical proposals for competitive tenders (RFPs) - an advantage.
Background in microwave communications, telemetry systems, and RF engineering at microwave frequencies - an advantage.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Edge-AI SOC Verification Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with architecture, software, design, and physical design stakeholders to make technical decisions and represent project status throughout the development process.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
10 years of experience working with hardware verification languages (e.g., SystemVerilog/Specman), design verification methodologies (e.g., UVM), and chip design flow.
4 years of experience in people management, developing employees.
Experience in leading chip verification teams through the full lifecycle from concept to delivery.
Experience in creating chip or subsystem design verification strategies and plans.
Preferred qualifications:
15 years of experience in verification of complex SoC/ASIC.
8 years of experience managing verification teams.
Experience in chip design/verification of AI/ML logic.
Experience with industry verification techniques, including complementary techniques such as Formal Verification, and Emulation.
Experience in Low Power Verification.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Edge-AI Verification Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
10 years of experience working with hardware verification languages (e.g., SystemVerilog/Specman), design verification methodologies (e.g., UVM) and chip design flow.
Experience in leading chip verification teams through the full lifecycle from concept to delivery.
Experience in creating chip or subsystem design verification strategies and plans.
Preferred qualifications:
15 years of experience in verification of complex SoC/ASIC.
8 years of experience managing verification teams.
Experience in verification of complex ISP (Image Signal Processing) designs.
Experience in chip design/verification of AI/ML logic.
Experience in Low Power Verification.
Experience with industry verification techniques, including complementary techniques such as Formal Verification, and Emulation.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Design For Test from DFT architecture to post silicon production support.
4 years of experience with people management.
Experience with DFT design and verification for multiple projects, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and common industry tools, DFT and Physical Design flows, and DFT verification flow.
Experience in leading DFT activities throughout the whole ASIC development flow.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in post-silicon Debug, test or product engineering.
Experience in Joint Test Action Group (JTAG) and Internal JTAG (iJTAG) protocols and architectures.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design AI Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead an edge AI IP design team including definition, implementation and deployment, and define IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
10 years of experience in design from microarchitecture through implementation using Verilog/SystemVerilog.
4 years of experience in managing teams and groups.
Experience working with system design principles for low latency, high throughput, security, and reliability.
Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Master's degree or PhD in Engineering or equivalent practical experience.
Experience in micro-architecture and design of complex AI modules, optimizing their power, performance and area.
Experience in leading chip development projects and teams, and execution.
Ability to motivate and focus on collaborative teams to achieve testing goals.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8843836
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in RTL design cycle from IP to SoC, from specification to production.
8 years of experience in execution teams management.
Experience in the following areas: RTL design, design quality checks, physical design aspects of RTL coding, and power.
Preferred qualifications:
Experience with synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with a scripting language like Python or Perl.
Experience with design for test and its impact on design and physical design.
Knowledge of one of the following areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, ARM processors family.
Knowledge of SoC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8847258
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חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Physical Design Lead, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Lead physical design of complex SoC to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the SoC flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
articipate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience in silicon implementation and chip integration.
Experience in ASIC development teams.
Experience in managing physical design teams working on digital designs that produce and deliver silicon.
Preferred qualifications:
Experience in extraction of design parameters and analyzing data trends.
Experience and breadth in engineering across physical design, top-level implementation, GDS tape-out.
Experience in top-level floor planning, block integration, static timing analysis, and sign-off.
Understanding of circuit design, device physics, and deep sub-micron technology.
Knowledge of delivery of high complexity silicon in technology process nodes.
Ability to lead cross-functional teams.
This position is open to all candidates.
 
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עדכון קורות החיים לפני שליחה
8847267
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
Responsibilities:
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
8 years of experience in technical leadership.
Experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Experience developing RTL for ASIC subsystems.
Preferred qualifications:
Experience working with design networking like: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience in TCP, IP, Ethernet, PCIE and DRAM including Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
Experience architecting networking switches, end points, and hardware offloads.
Understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8846925
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in RTL Design cycle from IP to SoC and from specification to production.
8 years of experience in Technical leadership.
Experience in the following areas: RTL Design, Design Quality checks, Physical Design aspects of RTL coding, and Power.
Preferred qualifications:
Experience with synthesis techniques to improve Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with Design For Test and its impact on Design and Physical Design.
Experience with a scripting language like Python or Perl.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, and ARM processors.
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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