דרושים » מדעים מדוייקים » Lead system Engineer

A global leader in medical-aesthetic technologies, with over 25 years of experience in energy-based devices (EBD). Over the years, we have evolved into an integrated aesthetic and wellness ecosystem that combines medical devices, injectables, diagnostics, and personalized skincare. The company operates in a dynamic, innovation-driven environment, merging advanced technology with deep clinical understanding to create holistic solutions for aesthetic clinics. Our headquarters are in Caesarea, Israel, with business operations in more than 100 countries worldwide. As part of our continued growth and innovation, we are looking for a Systems Engineer to join our multidisciplinary R&D team and play a key role in the development and integration of next-generation aesthetic platforms.
* Take part in defining system and subsystem requirements and maintain traceability from user needs to design inputs.
* Support system integration and bring-up of energy-based platforms and applicators, such as laser and diode modules, RF and ultrasound generators, cooling systems, and Embedded software.
* Contribute to risk management activities, including FMEA and hazard analysis
* Prepare and maintain design control documentation, such as specifications, DHF inputs and ECOs.
* Help prepare systems for safety and regulatory testing, such as IEC 60601 and IEC 60825 laser safety, together with developers, QA and RA.
* Investigate technical issues from production and the field, perform root cause analysis, and support CAPAs.
* Work closely with electrical, mechanical, optical, software, clinical, service, manufacturing and external subcontractor teams

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.

The Senior Silicon Photonics PIC Design Engineer will help build next-generation Photonic Integrated Circuits (PICs) that power high-performance optical interconnect solutions. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components, while contributing to optical test instrumentation for emerging semiconductor test markets.
As a member of the Silicon Photonics Engineering Staff, you will be a key player in the definition, implementation, and validation of complex automated test equipment that interfaces optical ports of silicon photonic devices at all stages of fabrication, from wafer probe to packaged test.
Lead the design, simulation, layout, and system-level testing of advanced silicon photonics components and Photonic Integrated Circuits.
Utilize simulation and design tools, including Ansys/Lumerical and Cadence Virtuoso, to design, validate, and optimize photonic designs.
Collaborate closely with design, layout, EIC, packaging, validation, quality, and system architecture teams to develop high-performance integrated photonic circuits and validate link performance.
Partner with fab and process engineers to define and optimize device design and implement process monitoring structures.
Develop test and qualification plans in coordination with validation and quality engineering teams.
Conduct rigorous testing and characterization of devices and PICs, including passive and active photonic components.
Engage in direct collaboration with silicon foundries to streamline processes and support successful tape-out execution.

In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.

You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.

Responsibilities:
As a member of the Package Design team, you will:

Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing support.

Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.

Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.

Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.

Assist in developing and improving package design methodologies, flows, and best practices.

Contribute to debugging, issue resolution, and package bring‑up activities as needed.

We are looking for a Technical support to join our growing robotics startup. This role is hands-on and multidisciplinary, involving installation, maintenance, troubleshooting, and on-site support of complex robotic systems. The systems combine mechanics, hardware, electronics, and advanced software, and require strong system-level understanding. The position includes work at our companys facilities as well as international travel, primarily for system installations, demos, and field troubleshooting. As part of our rapidly growing, small, motivated, and multi-disciplinary team, this position is the first dedicated role in its domain, providing a unique opportunity to contribute to a new area within the company.

Responsibilities
Maintain, test, and troubleshoot robotic systems at the companys facilities.
Install, calibrate, and commission robotic systems at customer and partner sites abroad.
Lead on-site system setup and troubleshooting during demos and early deployments.
Diagnose and resolve hardware, mechanical, and software issues in the field
Perform hands-on replacement and repair of mechanical and electromechanical components.
Work closely with R&D teams (software, mechanical, electrical, algorithms) to deeply understand the system.
Gather knowledge from internal engineering teams and apply it independently in the field.
Provide technical feedback from the field to improve system robustness and usability.
Document issues, procedures, and best practices.

In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities:

Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

We are seeking a high-driven, results-oriented multidisciplinary orchestrator to act as the primary catalyst for our development infrastructure. In this role, you will operate at the critical intersection of product strategy, hardware engineering, and lab operations, serving as the connective tissue that aligns disparate teams under a unified goal. You will be responsible for driving cross-functional alignment across the organization, effectively managing stakeholders with differing ownership to ensure infrastructure roadmaps scale alongside product milestones. This position requires a self-starter comfortable pushing for success in ambiguous environments, where you will translate high-level strategy into the tactical execution of the physical and virtual ecosystems that power our development lifecycle.

Your Impact

You will own the end-to-end lifecycle of infrastructure projects, ensuring that our Sanity Test Beds and development environments are optimized to meet aggressive product launch timelines. By bridging the gap between engineering roadmaps and infrastructure requirements, you will serve as the engine that ensures our teams have the right resources at the right time, regardless of technical or organizational complexity.

Key Responsibilities

Strategic Orchestration & Alignment

Unified Roadmap Integration: Translate complex product development roadmaps into long-term infrastructure requirements, driving cross-functional alignment between silicon milestones and lab availability.
Stakeholder Management: Act as the primary liaison between hardware engineering, software development, procurement, and lab operations; navigate competing priorities among stakeholders with differing ownership to keep teams synchronized.
Ambiguity Management: Proactively identify project roadblocks and navigate ambiguous environments to push critical-path dependencies to resolution.
Operational Velocity: Drive continuous improvement in infrastructure processes, identifying and removing friction to increase overall engineering velocity.
Operational Oversight & Execution

Strategic Capacity Planning: Lead high-stakes capacity management efforts, forecasting needs for power, rack space, and compute resources to proactively eliminate infrastructure bottlenecks.
Lifecycle Ownership: Oversee the full lifecycle of infrastructure projects-from initial procurement and technical specification through deployment, validation, and transition to operational readiness.
Visibility & Reporting: Drive the development of dashboards and reporting mechanisms to provide real-time visibility into infrastructure health, ensuring data-driven decision-making across the organization.
Vendor & Asset Optimization: Partner with cross-functional leadership to manage technical specifications, equipment lead times, and hardware lifecycles, ensuring a high-performance, cost-effective infrastructure footprint.

Spearhead innovative silicon architecture for AI infrastructure, guiding board design from concept through to mass production.

Act as the technical decision-maker for the project and collaborate with cross-functional teams in mechanics, thermal, PCB layout, and software/RTL.

Define product specifications, develop electrical schematics, and guide component selection.

Conduct hands-on testing in a lab environment and drive the PCB bring-up, characterization, and debugging stages.

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.