דרושים » תוכנה » Senior Real-Time Embedded Software Engineer (C++)

we are an agile defense-tech startup tackling the most complex challenges in counter-drone and uncrewed defense. With hundreds of combat-proven systems deployed by the IDF and global partners, we are now engineering the next generation of C-UxS (Counter-Uncrewed Systems). We leverage advanced electronic warfare and kinetic measures to detect and neutralize hostile threats. If you want to push technological boundaries while safeguarding Israel and our allies, join us at this pivotal stage of our growth.
This is a unique opportunity to join a company at a pivotal growth stage and help shape its products, culture, and future.
We are seeking a highly skilled C++ Software Engineer to join our fast-paced startup team. In this role you will join a high-performance, robust C++ software development team, with opportunities to contribute in Python for tooling, prototyping, and data processing. You will work on algorithmic challenges spanning GNSS, signal processing, computer vision, and geospatial data.
Responsibilities
Design and implement high-performance C++ software, with emphasis on real-time, efficient, and reliable code.
Develop and optimize algorithms related to GNSS, signal processing and geospatial analysis.
Use Python for prototyping, automation, and analysis tools.
Collaborate with cross-functional teams including hardware, research, and product.

Required Software Engineer
Job Description Summary
As a Software Engineer - PET Data Acquisition, you will join a highly specialized team developing the real-time software stack at the core of our PET/CT imaging systems.
Our software directly impacts image quality and system reliability, enabling clinicians worldwide to provide accurate diagnoses and life-saving care.
You will work on a distributed, high-performance C++ system running on Linux, responsible for configuring detector hardware, processing high-throughput data streams, and enabling seamless integration across the scanner ecosystem.
About the Team:
Our team develops the data acquisition platform powering our PET/CT scanners.
This system:
Configures and interfaces with detector hardware
Receives high-rate event streams via UDP
Performs real-time sorting and time-stamping of coincidence events
Manages acquisition state and persistence
Exposes control and monitoring APIs to clinical applications
The platform is a distributed, multi-process, multi-threaded C++ system running on Linux, designed for deterministic, high-performance operation under demanding workloads.
Key Responsibilities
Design and develop end-to-end data acquisition features, from low-level UDP capture and event processing through service layers and client APIs
Optimize and maintain performance-critical code paths, including:
Lock-free / low-contention data structures
Thread affinity and NUMA optimization
Zero-copy buffer management
Deterministic real-time execution
Enhance and maintain inter-process communication mechanisms, including shared memory, message queues, and service interfaces
Work with embedded persistence layers (SQL-based) for configuration, metadata, and runtime state
Collaborate closely with hardware, physics, and system teams to integrate new detector and system components
Develop unit and integration tests, and actively participate in code and design reviews
Troubleshoot complex cross-process issues using advanced debugging and profiling tools (e.g., gdb, perf, tcpdump, strace).

Required Staff Embedded Firmware Engineer, High Speed DSP
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Staff Embedded Firmware Engineer for High-Speed DSP, you will architect and define the low-level firmware and control loops powering the world's most advanced physical-layer communications silicon. Sitting at the critical intersection of digital signal processing (DSP), hardware-software co-design, and real-time systems, you will lead the development of adaptive algorithms, error correction (FEC), and link-telemetry frameworks. Your work will directly bridge the gap between high-performance hardware pipelines and our planetary-scale AI infrastructure, transforming complex communication systems theory into reliable, real-time silicon execution.
Responsibilities
Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, determining the optimal balance between hardware-fixed logic and programmable firmwarm.
Architect advanced "in-situ" monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real-time.
Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, managing real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration.
Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
Identify and de-risk hardware-software interface bottlenecks (e.g., register maps, driver latencies, and boot-up sequencing) that impact our AI infrastructure.

Are you passionate about systems programming at the intersection of hardware and software? Do you want your code to directly accelerate the world's largest AI training and inference workloads? The Elastic Fabric Adapter (EFA) Drivers team is looking for Software Development Engineers to design and implement the kernel drivers and userspace libraries that power high-performance networking for AWS's AI/ML and HPC infrastructure.

EFA is the custom network interface that enables thousands of GPUs and accelerators to communicate at near-wire-speed bandwidth and low latency, making it a critical enabler of both foundation model training and real-time inference serving at unprecedented scale. When customers train the next generation of large language models or serve billions of inference requests with tight latency SLAs on our EC2 P5, P6, or Trn instances, it's our driver stack that moves the data.

Key job responsibilities
- Design, develop, and optimize Linux kernel drivers (RDMA/EFA) and userspace provider libraries (rdma-core) that ship to millions of EC2 instances.
- Work directly with custom hardware - collaborate with chip designers to bring new silicon capabilities to life in software.
- Contribute to the upstream Linux kernel RDMA subsystem and rdma-core open-source project.
- Architect solutions for next-generation networking features: GPU-direct RDMA, adaptive routing, collective offloads, and multi-path transport.
- Build monitoring and automation tools to enhance driver testing for functionality, reliability, and performance.
- Own the full lifecycle: from initial hardware bring-up and feature enablement through testing, deployment, and production troubleshooting across the global AWS fleet.

We are the world leader in automotive and driving assistance systems, developing the world's most advanced software technologies and hardware architectures.
We are providing an end-to-end software solution for development and deploying features on its HW chip - EyeQ.
The compilers team is looking for a C++ Software engineer with a passion for low level optimizations and code analysis.
What will your job look like?
Develop and extend a compiler based on the LLVM infrastructure to support and optimize our EyeQ hardware.
Implement and improve middle‑end and back‑end compiler optimizations.
Analyze generated code to improve performance and efficiency.
Perform real-world benchmark analysis to find optimization opportunities.
Collaborate with chip architects on defining and supporting future hardware generations.

We are looking for a highly motivated backend software engineer specializing in creating high-scale, distributed backend systems.

You must demonstrate strong software engineering skills, excellent interpersonal communication, extreme ownership, and the ability to accept and give meaningful technical feedback.

You will be responsible for designing architecture, writing correct, robust code, maintaining and improving existing functionality, and shipping new features.

You will work as part of a Scrum-Agile cross-functional team and collaborate with front-end engineers, quality engineers, product managers, and more.

The platform you help us build will scale novel functionality to millions of Plus users worldwide.

Our team strives to set the bar for real-time, high-scale, mission-critical trading systems. We want to work with people who are excited by this goal and have the talent to deliver on it.

What Youll Do - Responsibilities

Design and build scalable, high-availability mission-critical systems and APIs
Drive the migration of large-scale, distributed trading services towards cloud-native microservices
Solve problems using distributed, asynchronous messaging
Tackle technical challenges - performance, fault-tolerance, security, and live production issues
Work closely with product, DevOps\SRE, and infrastructure teams - we practice full-cycle development where developers own and operate what they build.
Mentor Jr engineers as a Senior member of the team

Required Staff Design Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Our Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles.
Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5/6, PCIe Gen4/5, CDPHY, and MPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SIPI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions and automation, validation SW tools development, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.