Senior/ Staff Package Design Engineer

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8773855

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לפני 16 שעות

Senior/ Staff Physical Design Engineer - EMIR CAD

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) flow
Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate closely with Analog/SerDes designers to integrate current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis flow
Understand root-cause analysis for voltage drop violations and EM risks
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data.

Requirements:
Bachelor's or Master's degree in Electrical Engineering or a related technical field
5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
Strong proficiency in industry-standard EMIR tools flow development (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)
Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)
Basic understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
Proven Proficiency in Python in required, Tcl or Perl preferable for flow automation and data parsing
Deep understanding of the RedHawk tool, including efficient use of MapReduce and other Ansys proprietary capabilities (including potential use of ad-hoc SDC for context and LSO - Logic State Override)
Strong understanding of required inputs for creating Scenarios and Analysis Views
Deep understanding of standard cell and IP abstractions (APL, LIB, AVM), including IP waveform construction from PWL (sim2iprof)
Preferred Experience
Experience performing Chip-Package-System (CPS) thermal and power co-simulation
Familiarity with thermal analysis tools and their interaction with electrical performance
Experience working with sign-off criteria and margins for high-volume production chips
Basic understanding of timing and P&R
Good understanding of EM, including deterministic EM (DC, peak, RMS)
Basic understanding of statistical EM and reliability concepts (SEB, Blacks Equation, FIT, MTTF)
Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution.

This position is open to all candidates.

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8773899

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לפני 16 שעות

Staff/ Principal Physical Design Engineer - SoC EMIR Expert

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.
This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.
You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.
Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM)
Understand root-cause analysis for voltage drop violations and EM risks
Be responsible and go-to person for any IR related issues.

Requirements:
Bachelor's or Master's degree in Electrical Engineering or a related technical field
10+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)
Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)
Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
Ability to define and own EMIR methodologies
Capability to identify issues early in the project lifecycle (preferably with experience in sub-N5 TSMC technologies)
Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM
Thermal analysis, self-heat and Statistical EM proficiency
Preferred Experience
Familiarity with thermal analysis tools and their interaction with electrical performance
Experience working with sign-off criteria and margins for high-volume production chips
Good understanding of timing and P&R
Good understanding of packaging, top metal layers, MIM capacitor usage, and power distribution
Understanding of ESD (including full CDM closure) and latch-up
Strong Reliability knowledge
Ability to write TCL scripts for STA and Fusion Compiler (FC).

This position is open to all candidates.

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8773806

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לפני 16 שעות

Senior/ Staff Physical Design Engineer

חברה חסויה

Location: Haifa

Job Type: Full Time

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

Requirements:
Bachelor's degree in Electrical Engineering or related technical field
3+ years of hands-on experience in Physical Design at semiconductor companies
Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing
Experience working with advanced process technologies (7nm and below)
Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis
Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks
Preferred Qualifications
Experience with full-chip level implementation and integration
Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon
Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout
Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
Background in high-speed interface designs or connectivity protocols.

This position is open to all candidates.

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8773908

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לפני 16 שעות

Staff/ Principal Chip Top Physical Design Engineer

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.
As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.
Key Responsibilities
Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration.

Requirements:
B.Sc. or M.Sc. in Electrical Engineering
5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills
Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration
Preferred Qualifications
Deep understanding of Power & Noise analysis (EM/IR)
Experience with DFT (Design for Test) integration into the physical design flow
Background in high-speed interfaces or data center protocols.

This position is open to all candidates.

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8773841

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חברת השמה / כח אדם

7 ימים

Senior Power Integrity Engineer

חברה חסויה

Location: Ra'anana

Job Type: Full Time and Hybrid work

we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities:
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

Requirements:
B.Sc. or M.Sc. in Electrical Engineering.
5+ years of experience in Power Integrity, Hardware Design, or related disciplines.
Strong understanding of power delivery networks, decoupling methodologies, and target impedance concepts.
Hands-on experience with PI simulation tools such as:
Cadence Sigrity PowerSI / OptimizePI
Ansys SIwave
Ansys HFSS
PowerDC or equivalent
Experience designing high-layer-count PCBs for networking, telecom, server, or data-center products.
Knowledge of high-speed digital systems and interaction between Signal Integrity and Power Integrity.
Experience with multi-phase voltage regulators, power sequencing, and power management architectures.
Strong understanding of PCB materials, stackups, and manufacturing constraints.
Experience performing lab validation and correlation measurements.
Excellent problem-solving, communication, and teamwork skills.
Preferred Qualifications:
Experience with high-performance networking ASICs and switch silicon.
Familiarity with 112G/224G/448G PAM4 SerDes technologies.
Experience with Ethernet systems ranging from 400G to 1.6T and above.
Understanding of package-level PI and advanced packaging technologies.
Familiarity with optical networking platforms and co-packaged optics.
Experience with thermal and mechanical effects on PDN performance.
Knowledge of EMI/EMC considerations in high-density networking systems.
Experience working with ODMs, CMs, and global manufacturing partners.

This position is open to all candidates.

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8763922

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4 ימים

Senior Power Engineer

חברה חסויה

Location: Yokne`am

Job Type: Full Time

Our team in Yokneam, Israel is looking for a Senior Power Integrity Engineer to join the Hardware Board Design team and lead PI development of next-generation Network Adapters for high-speed communication products. Our Networking division delivers end-to-end InfiniBand and Ethernet connectivity for servers and storage, including adapter cards, switches, cables and software that power data centers, cloud, big data, Web 2.0 and high-performance computing workloads.

What you'll be doing:

Lead PI definition and implementation for board-level designs, from concept and architecture through validation, qualification and release to production.

Define the power core architecture and requirements and serve as the technical lead for all power-related performance and debug activities

Work closely with power supply vendors to align solutions with our product needs, and build and optimize configuration files for programmable regulators.

Own power delivery network (PDN) design for complex network adapter boards, including rail partitioning, decoupling strategy, VR selection and dynamic load support.

Perform system-level power integrity simulations (frequency and time domain) and co-simulation of circuits and PDN models to predict noise.

Create and maintain board PI design guidelines: stackup, materials, breakout, routing, decoupling and placement rules for layout teams and external partners.

Use advanced 2D/3D EM tools to model and optimize vias, planes, connectors, sockets and other interconnect elements for power integrity.

Perform lab characterization and correlation using VNA, TDR and high‑bandwidth oscilloscopes; refine models and design rules based on measurement data.

Requirements:
What we need to see:

B.Sc. in Electrical Engineering (or equivalent experience).

5+ years of industry experience in signal and/or power integrity for high-speed board or system designs.

Strong understanding of electromagnetics, transmission line theory, PDN behavior and their application.

Expert-level proficiency with EM and PI tools (for example, Ansys HFSS/Q3D/SIwave, CST, or equivalent) and SPICE-based time-domain simulations.

Proven experience in PDN analysis, including model generation, impedance targets, resonance mitigation and time-domain noise simulations.

Hands-on lab experience with VNA, TDR and oscilloscopes for PI/SI validation, de-embedding and model correlation.

Ability to work independently in an intense, multi-disciplinary environment with strong ownership and excellent interpersonal skills.

Ways to stand out from the crowd:

Deep experience designing PDNs for complex multilayer boards with high-current, low-voltage rails supporting advanced networking or compute ASICs.

Demonstrated background in PI co-simulation flows, PSIJ analysis and end-to-end system modeling (die-package-board).

Experience with scripting and data analysis using MATLAB, Python or C for simulation automation and large-signal data processing.

Exposure to advanced packaging and interconnect technologies (for example, TSV, high-speed connectors, advanced laminates).

Practical knowledge of PCB fabrication, product qualification flows and lab debug of complex high-speed boards.

This position is open to all candidates.

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8770084

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חברת השמה / כח אדם

01/07/2026

Senior SOC Quality and Reliability Engineer, Cloud

חברה חסויה

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required Senior SOC Quality and Reliability Engineer, Cloud
You will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the state-of-the-art SoCs that power these data centers by driving quality and reliability processes from the Integrated Circuit perspective. You will have an opportunity to create silicon and follow it into the field and back to drive improvements for the next-generations of chips.
As a part of this role, you will have an understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross-functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. You will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams within the larger organization.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive the strategic definition and development of Design-for-Reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge/latch-up (ESD/LU), biased highly accelerated stress test (b/HAST), etc.) and conduct in-depth failure analysis to resolve quality issues.
Extract and analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical quality and reliability models (including early life failure (ELF), time-dependent dielectric breakdown (TDDB), and negative bias temperature instability (NBTI)) to predict device failure mechanisms and lifetime behaviors.

דרישות:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field, or equivalent practical experience.
10 years of experience in IC silicon quality or reliability.
Experience leading the product reliability life-cycle from post-tapeout through high-volume manufacturing.
Experience working with semiconductor Complementary Metal-Oxide-Semiconductor (CMOS) technology, device physics, and failure mechanisms.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related field.
Expertise in statistical data analysis using tools such as JMP, Python, or JSL.
Familiarity with Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) techniques.
Proven track record with silicon reliability on process nodes and advanced packaging technologies.
Deep knowledge of Design-for-Reliability (DfR) rules and implementation techn המשרה מיועדת לנשים ולגברים כאחד.

עדכון קורות החיים לפני שליחה

8718507

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לפני 16 שעות

Silicon Technical Program Manager

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.
As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.
Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.

Requirements:
Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field
8+ years of experience in ASIC development and 3+ years in Program or Product Management or Technical/Engineering management
Proven leadership skills, with the ability to manage projects from technical details to the big picture
Experience in managing ASIC design flow, RTL, synthesis, functional verification, and physical layout
Experience in pre-silicon testing (Emulation, FPGA) and post-silicon validation is preferred
Excel in interpersonal communication, relationship building, and collaboration within cross-functional teams
Excellent organizational and leadership skills, and are capable of multitasking in a fast-paced environment
Preferred Qualifications
Familiarity with Networking technologies and concepts
Excellent strategic planning and communication skills, with a self-motivated focus on execution.

This position is open to all candidates.

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8773879

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חברת השמה / כח אדם

02/07/2026

SOC Quality and Reliability Engineer, Cloud

חברה חסויה

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

Required SOC Quality and Reliability Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Our data centers are the most advanced in the world. In this role, you will help build the SoCs that power these data centers by driving quality and reliability processes from the integrated circuit perspective. You will create silicon and follow it into the field (and back) to drive improvements for the next generations of chips.
You will have an understanding of IC flows, wafer processing, testing, qualification, yield, reliability, and failure analysis. You will work with various cross functional teams to develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute and test plans. Within the larger organization you will collaborate with global hardware quality and reliability teams, silicon design, validation and engineering teams.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive the strategic definition and development of design-for-reliability (DfR) guidelines, collaborating with cross-functional subject matter experts to integrate reliability into early design stages.
Define and lead the development of qualification hardware and test methodologies, managing internal teams and external vendors to ensure silicon and package verification.
Execute comprehensive silicon and package qualification programs (including high-temperature operating life (HTOL), early life failure rate (ELFR), electrostatic discharge/latch-up (ESD/LU), biased highly accelerated stress test (b/HAST), etc.) and conduct failure analysis to resolve quality issues.
Extract and analyze data from qualification programs, high-volume manufacturing, and field returns to identify failure mechanisms and trends for yield and reliability optimization.
Develop and implement physics-based statistical Quality and Reliability models (e.g., ELF, time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) to predict device failure mechanisms and lifetime behaviors.

Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field or equivalent practical experience.
8 years of experience in IC silicon quality or reliability.
Experience leading the product reliability lifecycle from post-tapeout through high-volume manufacturing.
Experience with semiconductor complementary metal-oxide-semiconductor (CMOS) technology, device physics, and failure mechanisms.
Preferred qualifications:
Master's degree in Electrical Engineering, Materials Science, or related field.
Expertise in statistical data analysis using tools such as JMP, Python, or JSL.
Knowledge of design-for-reliability (DfR) rules and implementation techniques.
Familiarity with electrical failure analysis (EFA) and physical failure analysis (PFA) techniques.
Track record with silicon reliability on process nodes and advanced packaging technologies.

This position is open to all candidates.

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8720958

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