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09/08/2026
Location: More than one
Job Type: Full Time
We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.
Requirements:
What we need to see:

Deep System-Level Perspective: Proven ability to understand complex computing or networking systems top-to-bottom, with a specific background in SmartNIC boards, chassis, or network tray architectures.

Device-Level Expertise: Hands-on experience debugging or architecting flows involving BMCs (e.g., OpenBMC), MCUs, CPUs, and complex networking ASICs.

Protocol Fluency: Strong working knowledge of modern platform management and security protocols, specifically MCTP, PLDM (Type 2, 5, etc.), SPDM, and NC-SI.

Hardware Interface Knowledge: Deep familiarity with board-level communication buses (I2C, I3C, SPI, USB) and system interconnects (PCIe architecture, including link states and reset mechanisms).

Analytical Documentation Skills: Exceptional ability to write clear, unambiguous technical specifications, state-machine descriptions, and sequence diagrams.

Experience Level: Typically requires a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, alongside 8+ years of relevant industry experience.

Ways to stand out from the crowd:

Experience with Redfish API definitions and OOB network infrastructure.

Familiarity with hardware root of trust (HRoT / eROT) concepts and secure boot architectures.

Experience with PLDM firmware update bundle packaging and update agent implementation.

Experience with production line tooling, factory provisioning, and manufacturing test flows.
This position is open to all candidates.
 
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09/08/2026
Location: Yokne`am
Job Type: Full Time
We are seeking a Senior System Management Architect to join our growing team. You will be the resident expert for system management, ensuring that AI factory management components (BMCs, MCUs, CPUs, network switches and CPLDs) operate in perfect unison. You will own the lifecycle management specifications for AI factory platforms - from factory provisioning to day-one deployment. If you enjoy studying a high-level system diagram and then immediately diving into the system-level buses and interface signals topology and the associated host management protocols modeling required to make it work, this role is for you.



What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery, and reset flows for AI factory sub-systems.
Ensure system-level architectural alignment and orchestrate seamless coordination between all the AI-Factory building blocks: GPU, DPU, CPU, Switch ASIC, NIC ASIC, BMC, and peripheral components.

Protocol Implementation & Guidance: Specify the use of standard management protocols (Red-Fish, NSM, PLDM, SPDM, MCTP, NC-SI) across sub-system interfaces to implement the management tasks.

Hardware/Software Intersect: Define system-level hardware and software behavior, including CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets).

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate with Production, Hardware and Firmware Engineering, ASIC FW/Driver teams, SW/NOS teams and QA to translate architectural specifications into implementable, testable solutions.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide development and factory production.
Requirements:
What we need to see:

Deep System-Level Perspective: Proven ability to understand complex computing or networking systems top-to-bottom, with a background in networking architectures and efficiency and power saving methods.

Protocol Fluency: Strong working knowledge of modern platform management and security protocols.

Hardware Interface Knowledge: Familiarity with board-level communication buses (I2C, I3C, SPI, USB) and system interconnects (PCIe architecture, including link states and reset mechanisms).

Analytical Documentation Skills: Exceptional ability to write clear, unambiguous technical specifications, state-machine descriptions, and sequence diagrams.

Experience: BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 5+ years of relevant industry experience.



Ways to stand out from the crowd:

Experience with power-saving methods.

Background with Redfish RESTful API definitions and OOB network infrastructure.

Familiarity with hardware RoT concepts and secure boot architectures.

Experience with production line tooling, factory provisioning, and manufacturing test flows.

Background in networking principles, Switch, NIC/SmartNIC data-plane and offload operations, or high-speed data center topologies.
This position is open to all candidates.
 
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09/08/2026
Job Type: Full Time
We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.
Requirements:
What We Need To See:

B.Sc. or M.Sc. in Computer Engineering, Computer Science, Electrical Engineering, or equivalent experience.

9+ years of experience in networking, system software, embedded software, firmware, or datacenter infrastructure.

Proven experience in software architecture, or technical leadership roles.

Deep understanding of networking concepts and protocols such as Ethernet, TCP/IP, RDMA/RoCE, congestion control, QoS, virtualization overlays, and traffic management.

Strong background with DPUs, SmartNICs, or other high-performance networking devices.

Experience with system management, provisioning, monitoring, telemetry, diagnostics, or lifecycle-management flows.

Familiarity with management protocols and frameworks such as Redfish, PLDM, MCTP, IPMI, gNMI, SNMP, Netconf, REST, or gRPC-based APIs.

Ability to lead cross-functional architecture discussions across software, firmware, hardware, validation, product, and customer-facing teams.

Excellent written and verbal communication skills, including the ability to create clear architecture documents and present trade-offs.


Ways To Stand Out From The Crowd:

Experience defining software architecture for DPU products, including management, telemetry, QoS, performance, security, virtualization, or offload features.

Hands-on background with Linux networking, device drivers, firmware, embedded Linux, BMC software, DOCA, DPDK, OVS or Kubernetes networking.

Experience with performance counters, profiling tools, eBPF, Prometheus, Grafana, dashboards, heat maps, or large-scale telemetry systems.

Experience in defining and developing GAI-based analysis tools to extract insights from telemetry data and streams.

Background in RAS, diagnosability, serviceability, field failure analysis, production debug, or customer escalation handling.
This position is open to all candidates.
 
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09/08/2026
Location: More than one
Job Type: Full Time
We are looking for a Senior Software/Firmware Architect to join our Host Management group. The architect will develop the next-generation management solutions for our networking infrastructure environments. We are a team that values technical depth, clear ownership, and respectful collaboration. We believe great architecture is built through curiosity, rigorous thinking, and close partnership across disciplines. We welcome architects who bring different perspectives, ask hard questions, and want to build systems that matter at scale.

Our team handles the software and firmware that support host management flows throughout platform control software, baseboard management controllers, hardware interfaces, data monitoring, restoration processes, energy regulation, module management, and system orchestration. In this role, you will develop architecture, lead multi-departmental teams, and convert complex platform requirements into scalable, reliable, production-ready solutions.

What you will be doing:

Lead architecture definition for Host Management SW and FW across our networking platforms.

Define system flows across host software, embedded firmware, BMC, device firmware, and hardware interfaces.

Guide the development of architecture for telemetry, recovery, power management, module management, firmware update flows, and control protocols.

Convert product, customer, and platform needs into clear technical specifications and implementation plans.

Work closely with SW, FW, HW, validation, program, architecture, and customer-facing teams.

Provide technical leadership to engineers implementing complex cross-domain features.

Own architecture documentation and communicate technical direction clearly to engineering and leadership.
Requirements:
What we need to see:

B.Sc. or M.Sc. in Computer Science, Electrical Engineering, Computer Engineering, or equivalent experience.

12+ years of experience in system software, firmware, embedded systems, platform management, or networking systems.

Strong background in SW/FW architecture for complex systems.

Deep understanding of firmware, embedded software, Linux, BMC, host interfaces, and system-level debug.

Experience with protocols or technologies such as PLDM, MCTP, NC-SI, PCIe, I2C, USB, CMIS, Ethernet, InfiniBand, or NVLink.

Strong communication skills and experience writing architecture documents, specifications, and technical proposals.


Ways to stand out from the crowd:

Experience with NVIDIA networking products, DPUs, NICs, Switches, CPO/NPO, or hyperscale data center platforms.

Background in host management, BMC architecture, platform firmware, data monitoring, system restoration, power/thermal management, or module management.

Experience defining SW/FW interfaces across large multi-team programs.

Hands-on background in bring-up, validation, production debug, or customer issue resolution.

Track record of leading architecture from early definition through successful product delivery.
This position is open to all candidates.
 
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04/08/2026
Location: Yokne`am
Job Type: Full Time
We are looking for a skilled Software Developer with strong hardware knowledge to join our team developing production test solutions for optical transceivers and networking products. Our team builds the software and test infrastructure used on production lines to validate our optical and interconnect products. The work combines instrument automation, low-level software development, and direct control of custom hardware. You will work with optical instruments such as power meters, variable optical attenuators, and laser sources, as well as custom test boards used to control and communicate with the device under test (DUT).

This is a hands-on, technically deep role that spans the entire development lifecycle-from hardware bring-up and debugging to validation, deployment, and production support. As a technical focal point, you will work at the intersection of hardware and software, collaborating with electrical, hardware, thermal, mechanical, and software engineers to deliver robust and scalable test solutions across multiple production lines and products.

What Youll Be Doing:

Design and develop production test systems for optical transceivers, networking hardware, and interconnect products.

Develop software that controls optical test instruments, custom test boards, and other hardware components.

Write low-level drivers and hardware-control software in C and C++, and integrate native code with higher-level C# applications through DLL wrappers.

Read and interpret electrical schematics, block diagrams, datasheets, timing requirements, and hardware specifications.

Lead hardware bring-up, validation, and deployment of test solutions in production environments.

Debug complex hardware-software integration issues using oscilloscopes, logic analyzers, software tools, and hardware communication interfaces such as I2C, SPI, and UART.

Investigate failures, identify root causes, and implement reliable corrective solutions.

Collaborate with cross-functional teams to translate hardware requirements into software interfaces and automated test procedures.

Take technical ownership of projects from initial concept and prototype development through production release and ongoing support.

Improve test coverage, system reliability, maintainability, and scalability across multiple products and production lines.
Requirements:
What We Need to See:

Bachelors or masters degree in Electrical Engineering, Computer Engineering, Software Engineering, or a related field with significant hardware, electronics, or software experience.

4+ years of hands-on experience in software development, hardware-software integration, low-level driver development, firmware, or automated hardware testing.

Strong programming experience in one or more of Python, C#, C, or C++, with practical experience developing software that interfaces with hardware.

Experience reading and interpreting electrical schematics, block diagrams, hardware datasheets, and technical specifications.

Hands-on experience debugging hardware and software using laboratory instruments and software debugging tools.

Strong problem-solving skills and the ability to diagnose sophisticated hardware-software interaction issues.

Demonstrated technical ownership of projects, including development, integration, validation, and production deployment.

Excellent communication and collaboration skills, with the ability to work effectively across hardware and software teams.

Ways To Stand Out from the Crowd:

Experience with optical test equipment such as power meters, variable optical attenuators, laser sources, optical switches, or similar instruments.

Hands-on experience with PCIe, I2C, SPI, UART, Ethernet, or other hardware communication protocols.

Experience developing device drivers or hardware-interface software for Windows or Linux.

Experience wrapping native C/C++ libraries for use in managed .NET or C# applications.
This position is open to all candidates.
 
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04/08/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for a talented and experienced Firmware Architect to join our Network Adapter Firmware team in Yokneam.

As part of our technical leadership team, you will define the firmware architecture for next-generation networking devices and drive design of innovative technologies powering the world biggest AI Platforms, cloud computing, HPC, storage, and automotive platforms.

The Network Firmware team develops cutting-edge firmware that enables the world's largest cloud providers and enterprises to deliver high-performance, reliable, and secure networking solutions. Working alongside exceptional engineers across the globe, you'll thrive in a dynamic, collaborative, and fast-paced environment while solving some of the industry's most challenging technical problems.

What you'll be doing:
Collaborate closely with Hardware, Software, and System Architecture teams to define end-to-end solutions.
Define the firmware architecture for new products and features at the core of our NIC firmware.
Lead the design and implementation of strategic technologies, including functional safety, security, and next-generation networking capabilities.
Mentor and technically guide R&D engineers throughout architecture, design, and implementation.
Drive technical direction across multiple teams while ensuring scalable, maintainable, and high-quality firmware architecture.
Requirements:
What we are looking for:
B.Sc. in Computer Science, Computer Engineering, Electrical Engineering, or equivalent practical experience.
10+ years of firmware or embedded software development experience.
4+ years of technical leadership experience (Technical Lead, Architect, or Technical Manager).
Excellent understanding of algorithms, data structures, and software design principles.
Strong analytical, debugging, and problem-solving skills.

Ways to stand out from the crowd:
Experience with networking protocols and high-performance networking.
Experience developing real-time or embedded systems.
Experience designing large-scale firmware architectures.
Familiarity with Agile development methodologies.
Experience with security technologies or safety-critical systems.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required RTL Design Technical Lead, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of Application-Specific Integrated Circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
8 years of experience in technical leadership.
Experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Experience developing RTL for ASIC subsystems.
Preferred qualifications:
Experience working with design networking like: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience in TCP, IP, Ethernet, PCIE and DRAM including Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
Experience architecting networking switches, end points, and hardware offloads.
Understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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04/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are seeking a Network Solution Verification Manager to join our R&D organization, leading the validation of our customer-facing networking solutions at scale using a state-of-the-art End-to-End (E2E) simulation cluster environment.

In this role, you will build and lead a team of validation engineers, owning the strategy, methodology, and execution of simulation-based validation frameworks that ensure our networking solutions meet the highest standards of quality, scale, and real-world applicability before reaching customers.


What you'll be doing:
Leading and managing a team of network validation engineers responsible for end-to-end validation of our customer-facing networking solutions at scale, using a dedicated E2E simulation cluster environment.
Defining the overall validation strategy and roadmap - establishing simulation methodologies, test coverage frameworks, and quality gates that align with product milestones and customer use cases.
Pioneering the use of agentic AI flows within the validation organization - leading the team to design, build, and operate AI-driven agents capable of autonomously performing regression analysis, identifying coverage gaps, generating new test cases, and implementing validation code. These agentic workflows will continuously learn from simulation results and product changes, dramatically accelerating the team's ability to scale test coverage and respond to emerging quality signals without manual intervention.
Overseeing the design and continuous improvement of automated regression suites for networking protocols and large-scale simulation runs, ensuring scalable, repeatable, and high-confidence validation outcomes.
Establishing a rigorous regression analysis culture - guiding the team in identifying trends, root causes, and systemic coverage gaps, and ensuring timely resolution in collaboration with engineering stakeholders.
Serving as the primary validation partner to Design, Architecture, and NCS teams - translating solution requirements into simulation scenarios, providing early-cycle quality feedback, and influencing product direction.
Analyzing customer-reported networking solution issues, driving test gap analysis, and ensuring robust regression coverage that prevents recurrence.
Staying current with emerging networking standards, simulation technologies, and industry best practices to continuously evolve the team's validation capabilities.
דרישות:
What we need to see:
B.Sc. degree or equivalent experience in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
3+ years of experience in a leadership or management role, leading software or hardware validation/test engineering teams.
7+ years of overall experience in network validation, network testing, or systems verification.
Proven track record of building and executing test automation strategies for network or distributed systems at scale, with hands-on background in Python-based automation.
Strong understanding of regression analysis methodologies - ability to drive actionable conclusions from large-scale test result datasets and translate them into engineering improvements.
Demonstrated ability to collaborate cross-functionally with architecture, design, and product teams in a fast-paced, multi-timezone environment.
Strong verbal and written communication skills, with experience presenting validation strategies and quality metrics to senior leadership.


Ways to stand out from the crowd:
Deep understanding of networking protocols and architectures (e.g., BGP, EVPN, VXLAN, RDMA/RoCE, Ethernet, IP routing, L2/L3 switching).
Experience with network simulation or emulation environments (e.g., Containerlab, GNS3, SONiC testbeds, or equivalent platforms) and the ability to guide teams in leveraging them effectively.
Experience managing validation of data center networking solutions or hyperscale network environments (spine-leaf, fat-tree, or Clos top#EN המשרה מיועדת לנשים ולגברים כאחד.
 
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03/08/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
FUSE is building the next generation of autonomous defense technology: intelligent robotic systems and multi-domain platforms that redefine how forces operate, sense, decide, and act. Our systems work alongside human operators for surveillance, strike, and mission support
At FUSE, we bring together industry pioneers into one agile organization under our company, combining the speed, sense of ownership, and innovation culture of a startup with the manufacturing power and operational strength of a global defense leader. Our teams own the full stack end-to-end, from mechanical design, hardware, and embedded systems to robotics, autonomy, AI, and real-time multi-platform decision-making
Here, technology goes from concept to operational deployment. Fast. Your work doesn't sit in a backlog. It takes off
We are looking for
We're looking for a Senior System Engineer to own payload integration for autonomous platforms. You'll architect communication interfaces between EO/IR sensors, laser rangefinders, and flight systems. Your work directly enables precision targeting and real-time intelligence for MUM-T operations
In this role you will
Define system architecture for payload integration on autonomous platforms
Design and validate communication interfaces between EO/IR sensors, LRF lasers, and mission computers
Own requirements flow-down from platform level to payload subsystems
Lead technical reviews and interface control document development
Troubleshoot system-level issues across hardware, firmware, and software boundaries
Collaborate with hardware, software, and flight test teams to validate end-to-end performance
Support flight tests and analyze system performance data
Drive trade studies for payload capabilities and mission configurations.
Requirements:
B.Sc. in Electrical Engineering, Computer Engineering, or related field
5+ years in system engineering for defense or aerospace systems
Hands-on experience with electro-optical and infrared sensors
Strong understanding of communication protocols and interface design
Proven ability to work across multidisciplinary engineering teams
Experience with requirements management and verification processes
Experience with laser systems or rangefinders - advantage
Background in UAV or robotic platforms - advantage
Familiarity with MIL-STD-1553, ARINC, or similar avionics protocols - advantage
This is your chance to be a part of a new and exciting opportunity, work on complex, high-stakes systems, push the boundaries of autonomy and robotics, and build technology that makes an instant impact
If you're looking to move fast, think big, and shape what comes next, we want you with us
Only relevant applications will be answered**.
This position is open to all candidates.
 
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09/08/2026
חברה חסויה
Location: More than one
Job Type: Full Time
The System-On-Chip (SOC) group is looking for a strong RTL Design Engineer to own the SOC clocking logic for our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will own the clock generation, distribution, and control logic for the entire chip - PLL and reference clock integration, clock muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.

This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams.

What you'll be doing:

Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out.

Defining and implementing the SOC clock and reset architecture together with the micro-architecture team - collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design.

Owning clock domain crossing infrastructure and CDC closure across the SOC.

Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power.

Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness.

Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.

Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks.

Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable.

Supporting emulation, firmware, and post-silicon bring-up customers of your design.
Requirements:
What we need to see:

B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.

3+ years of relevant experience in RTL/logic design.

Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation.

Experience taking a design from micro-architecture specification through verification and physical implementation.

Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing.

Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis).

Great teammate with strong communication skills across micro-architecture, DV, and backend teams.


Ways to stand out from the crowd:

Passion for quality, and a track record of clean deliveries to physical design, DV, emulation, firmware, and other downstream customers.

Prior ownership of SOC-level clocking or reset architecture on a taped-out chip.

Experience with PLL/clock generator integration and clock tree constraint development with backend teams.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Staff Embedded Firmware Engineer, High Speed DSP
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Staff Embedded Firmware Engineer for High-Speed DSP, you will architect and define the low-level firmware and control loops powering the world's most advanced physical-layer communications silicon. Sitting at the critical intersection of digital signal processing (DSP), hardware-software co-design, and real-time systems, you will lead the development of adaptive algorithms, error correction (FEC), and link-telemetry frameworks. Your work will directly bridge the gap between high-performance hardware pipelines and our planetary-scale AI infrastructure, transforming complex communication systems theory into reliable, real-time silicon execution.
Responsibilities
Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, determining the optimal balance between hardware-fixed logic and programmable firmwarm.
Architect advanced "in-situ" monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real-time.
Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, managing real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration.
Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
Identify and de-risk hardware-software interface bottlenecks (e.g., register maps, driver latencies, and boot-up sequencing) that impact our AI infrastructure.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
10 years of industry experience in embedded systems/firmware, communication systems engineering, or digital signal processing (DSP) development.
Experience developing embedded software (C/C++) for high-speed physical-layer interfaces (PHY), digital transceivers, or communication subsystems.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
Expertise in Forward Error Correction (FEC) algorithms and advanced modulation schemes.
Track record defining firmware framework specifications, register maps, and Silicon Lifecycle Management telemetry for high-volume networking or AI silicon.
Background in wireless communications with deep domain knowledge of channel modeling, noise mitigation, and digital transceiver architectures.
This position is open to all candidates.
 
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