דרושים » הנדסה » Senior ASIC Design Engineer

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Junior ASIC Design Engineer, you won't just build chips - you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a Staff DFT Engineer at our company, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.
Key Responsibilities
DFT Architecture & Strategy
Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
​DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies
Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a DFT Engineer at our company, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.
Key Responsibilities
DFT Architecture & Strategy
Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices
Test Pattern Development & Optimization
Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation
Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.
As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.
Key Responsibilities
Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle-from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams.
This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions.
Key Responsibilities
DFT Architecture & Technical Leadership
Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies
Lead DFT planning, specification, and quality tracking across the project lifecycle
Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout
Execution Across the Full Lifecycle
Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels
Own end-to-end DFT activities from specification through silicon bring-up and production support
Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements
Methodology & Cross-Functional Impact
Develop and drive scalable DFT methodologies, flows, and automation frameworks
Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness
Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.
As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.
Key Responsibilities
Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects.