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23/06/2026
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מיקום המשרה: יקנעם ותל אביב יפו
סוג משרה: משרה מלאה
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06/08/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a Full-Chip verification & Integration Engineer to join our FullChip Switch Silicon team. As part of NVIDIAs Networking business unit, you will work alongside passionate and highly skilled engineers building the next generation of state-of-the-art switch silicon chips. This is a unique opportunity to grow in a technically rich environment and gain broad system-level exposure, and contribute to cutting-edge devices that deliver world-class bandwidth, throughput, and latency.

In this role, you will help integrate and validate complex full-chip flows at the system level, working across multiple engineering domains and learning how advanced silicon products come together from architecture to execution.

What you'll be doing:

Work in a Full Chip verification team that is responsible to integrate and verify our Switch products at system level.

Work closely with multiple teams within the organizations such as Architecture, u-arch, Firmware and all switch units and Ips.

Play a key role in validating the most complex end-to-end chip flows, gaining hands-on experience with system behavior, cross-block interactions, and real product-level scenarios.

Use modern AI-powered engineering tools and automation techniques as part of your day-to-day development and debug workflow.

Learn from experienced engineers in a collaborative environment that encourages technical growth, ownership, and continuous improvement.
Requirements:
What we need to see:

Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience

1+ years of experience in verification, advantage for FullChip/SoC

Knowledge in network protocols - advantage

Background in Specman - advantage

A team player with good communication and interpersonal skills

Strong analytical and debugging skills, with eagerness to learn in a fast-paced engineering environment.


Ways to stand out from the crowd:

Exposure to SoC or Full-Chip verification flows.

Familiarity with scripting or automation using Python, Perl, or similar tools.

Understanding of pre-silicon validation, emulation, or post-silicon concepts.

Interest in high-performance networking, switching architectures, or large scale system design.
This position is open to all candidates.
 
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04/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are seeking a Network Solution Verification Manager to join our R&D organization, leading the validation of our customer-facing networking solutions at scale using a state-of-the-art End-to-End (E2E) simulation cluster environment.

In this role, you will build and lead a team of validation engineers, owning the strategy, methodology, and execution of simulation-based validation frameworks that ensure our networking solutions meet the highest standards of quality, scale, and real-world applicability before reaching customers.


What you'll be doing:
Leading and managing a team of network validation engineers responsible for end-to-end validation of our customer-facing networking solutions at scale, using a dedicated E2E simulation cluster environment.
Defining the overall validation strategy and roadmap - establishing simulation methodologies, test coverage frameworks, and quality gates that align with product milestones and customer use cases.
Pioneering the use of agentic AI flows within the validation organization - leading the team to design, build, and operate AI-driven agents capable of autonomously performing regression analysis, identifying coverage gaps, generating new test cases, and implementing validation code. These agentic workflows will continuously learn from simulation results and product changes, dramatically accelerating the team's ability to scale test coverage and respond to emerging quality signals without manual intervention.
Overseeing the design and continuous improvement of automated regression suites for networking protocols and large-scale simulation runs, ensuring scalable, repeatable, and high-confidence validation outcomes.
Establishing a rigorous regression analysis culture - guiding the team in identifying trends, root causes, and systemic coverage gaps, and ensuring timely resolution in collaboration with engineering stakeholders.
Serving as the primary validation partner to Design, Architecture, and NCS teams - translating solution requirements into simulation scenarios, providing early-cycle quality feedback, and influencing product direction.
Analyzing customer-reported networking solution issues, driving test gap analysis, and ensuring robust regression coverage that prevents recurrence.
Staying current with emerging networking standards, simulation technologies, and industry best practices to continuously evolve the team's validation capabilities.
דרישות:
What we need to see:
B.Sc. degree or equivalent experience in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
3+ years of experience in a leadership or management role, leading software or hardware validation/test engineering teams.
7+ years of overall experience in network validation, network testing, or systems verification.
Proven track record of building and executing test automation strategies for network or distributed systems at scale, with hands-on background in Python-based automation.
Strong understanding of regression analysis methodologies - ability to drive actionable conclusions from large-scale test result datasets and translate them into engineering improvements.
Demonstrated ability to collaborate cross-functionally with architecture, design, and product teams in a fast-paced, multi-timezone environment.
Strong verbal and written communication skills, with experience presenting validation strategies and quality metrics to senior leadership.


Ways to stand out from the crowd:
Deep understanding of networking protocols and architectures (e.g., BGP, EVPN, VXLAN, RDMA/RoCE, Ethernet, IP routing, L2/L3 switching).
Experience with network simulation or emulation environments (e.g., Containerlab, GNS3, SONiC testbeds, or equivalent platforms) and the ability to guide teams in leveraging them effectively.
Experience managing validation of data center networking solutions or hyperscale network environments (spine-leaf, fat-tree, or Clos top#EN המשרה מיועדת לנשים ולגברים כאחד.
 
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09/08/2026
Location: Yokne`am
Job Type: Full Time
We are looking for a best-in-class Senior Full-Chip Verification Engineer with a strong infrastructure mindset to join our Networking Silicon team. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level, while also driving the evolution of the simulation infrastructure powering our verification flows. You will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the world's most advanced data centers, in a meaningful, growing environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Simulation Infrastructure & Acceleration: Identify bottlenecks in the verification flow and engineer creative solutions - building frameworks, optimizing regressions, and accelerating simulation throughput through innovative tooling.

Multi-Language Development: Work across a diverse technology stack (SystemVerilog/UVM, Specman, Python, C/C++, scripting) - writing code and solving problems at every layer, from RTL testbenches to infrastructure utilities and automation.

System-Level Debug & Analysis: Gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance.

AI-Enhanced Development: Accelerate development by leveraging cutting-edge AI coding tools and frameworks - applied to both verification and infrastructure challenges.

Cross-Team Collaboration: Work closely with multiple teams within organizations such as Architecture, u-arch, Firmware and all units inside the NIC.
Requirements:
What we need to see:

Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.

8+ years of experience in verification, HW simulation, or infrastructure development for silicon projects.

Infrastructure mindset - a proven ability to enhance and scale the systems that drive verification: regression frameworks, simulation performance, tooling, and flow automation.

Creativity and proactivity - an innovation mindset with a proactive approach to adopting new methodologies and coding tools to solve complex challenges.

Strong debugging, problem-solving, and analytical skills.

A team player with good communication and interpersonal skills.


Ways to stand out:

Experience leveraging AI tools for verification automation or infrastructure acceleration.

Experience working in multi-language environments.
This position is open to all candidates.
 
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09/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.
As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.
Key Responsibilities
Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects.
Requirements:
Bachelor's degree in Electrical Engineering or a related technical field
4+ years of hands-on experience in Formal Verification within semiconductor companies
Deep expertise in formal verification methodologies, tools, and flows
Strong understanding of RTL design and verification principles
Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)
Excellent communication skills, strong analytical thinking, and a proactive, "can-do" approach to problem-solving
Preferred Qualifications
Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle
Experience with SystemVerilog UVM-based design verification
Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe)
Background in high-speed serial interface verification.
This position is open to all candidates.
 
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03/08/2026
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for a Chip Design Verification Engineer to develop the next generation of DFT technologies.

As a Chip Design Verification Engineer in the DFT team at NVIDIA, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.

As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
BSc. in Electrical Engineering or Computer engineering, or equivalent experience.

3+ years of practical verification experience.

Experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, Verilog, debug tools like Simvision/Debussy).

Experience with Specman is a plus.

Good understanding of RTL design (Verilog).

Strong debugging, problem solving and analytical skills.

Excellent communication and social skills.

Ability to work in a geographically diverse team environment.

Self motivated, independent and target oriented.
This position is open to all candidates.
 
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06/08/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs.

Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.

A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary.

Proficiency using Python, Tcl, Shell, Make scripting.

Experience in Linux environments.

AI tools orientation or alternatively a desire to learn.

Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus).

Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)

Self-motivation, attention to detail, and good interpersonal skills.


Ways to stand out from the crowd:

Experience with data collection and analysis

Experience in methodology definition / flow owner of Full-chip / Place and Route

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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11/08/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We are looking for exceptional engineers to join the top-tier team developing the next generation semiconductor platform based on a revolutionary architecture. You will participate in design activities, working on the next generation of our products.

As a Chip Design Engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities:
* Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.
Requirements:
Basic Qualifications
- 4+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- BSc in Electrical Engineering/Computer Engineering/Computer Science.

Preferred Qualifications
- Background in protocols (AXI, CHI, DDR, Networking, PCIe).
- knowledge of Network-on-Chip (NOC) architecture.
- Experience with coherent and non-coherent fabric design.
- Experience with the entire SoC cycle - Synthesis / STA / CDC / Lint.
- Experience with Design Automation tools and techniques.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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22/07/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.
Requirements:
Basic Qualifications
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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04/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We seek an AIR SaaS Platform Verification Manager to join our Air - the Data Center Digital Twin. As a AIR SaaS Platform Verification Manager, you will have to work closely with our development and architecture teams responsible for our Air and gain a deep understanding of our products and technologies. and gain a deep understanding of our products and technologies.


What youll be doing:
Leading and managing the verification team responsible for AIR SaaS Platform, ensuring high quality delivery of both the backend and the frontend, working closely with diverse cross-functional teams to effectively implement, improve and automate verification strategies for cloud and on-prem deployments.
Work with the DevOps to integrate the verification pipeline into the CI/CD and use your expertise in Python and frontend testing to identify the most effective verification methodologies and tools, suggest reporting process improvement.
Analyze customer-reported issues, identify test gaps, and ensure robust regression coverage.
Foster a culture of innovation, quality, ownership, and accountability.
Support team members with career development plans and achievable growth goals.
Drive improvements for performance, quality, stability around SW acceleration solutions.
Stay up to date with industry standard methodologies, new technologies, and emerging trends in software verification.
Requirements:
What we need to see:
B.Sc. degree or equivalent experience in Engineering/Computer Science/related field.
3+ years of experience in a leadership role, managing of software development teams.
5+ overall years of experience in software development and testing.
Strong understanding of SaaS architectures.
Hands-on experience testing Python/Django (including REST APIs) and proven experience with frontend testing (UI automations using end-to-end testing frameworks such as Selenium, Playwright or Cypress).
Hands-on experience with Infrastructure as a Service (IaaS).
Comfortable working in a fast-paced, highly collaborative multi timezone environment.
Strong verbal and written communication skills.
Intrinsically motivated with a desire for automation programming.


Ways to stand out from the crowd:
Background in developing virtualization solutions using technologies like QEMU and Docker.
Knowledge of Linux networking and understanding of networking concepts and protocols.
Proficiency in Infrastructure as Code (IaC) frameworks.
This position is open to all candidates.
 
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10/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.
Requirements:
Bachelor's degree in Electrical Engineering or related technical field
3+ years of proven experience in ASIC verification within the semiconductor industry
Hands-on experience developing components within complex verification environments using SystemVerilog
Strong working knowledge of standard verification methodologies, specifically UVM
Sharp analytical mind with passion for debugging and technical problem-solving
Excellent communication skills with ability to thrive in collaborative R&D environments
Preferred Qualifications
Master's degree in Electrical Engineering or related field
Familiarity with Formal Verification or Emulation flows
Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks
Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL
Experience with assertion-based verification and constrained-random testing
Background in connectivity or networking silicon verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8775143
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