Senior Physical Design Engineer

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8702545

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לפני 5 שעות

Senior Full Chip Layout and Physical Verification CAD Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs.

Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.

A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary.

Proficiency using Python, Tcl, Shell, Make scripting.

Experience in Linux environments.

AI tools orientation or alternatively a desire to learn.

Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus).

Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)

Self-motivation, attention to detail, and good interpersonal skills.

Ways to stand out from the crowd:

Experience with data collection and analysis

Experience in methodology definition / flow owner of Full-chip / Place and Route

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.

This position is open to all candidates.

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8703737

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לפני 10 שעות

Physical Design Backend Engineer

חברה חסויה

Location: Yokne`am

Job Type: Full Time

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate.

This position is open to all candidates.

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8703271

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לפני 6 שעות

Senior Physical Design Layout Engineer

חברה חסויה

Location: More than one

Be'er Sheva

Tel Aviv-Yafo

Yokne`am

Job Type: Full Time

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering.

You should have at least 5+ years of hands-on layout experience, demonstrating your proven expertise.

A strong background in Physical Verification methodology, including ERC, LVS and DRC, is necessary.

In-depth knowledge of advanced silicon process technologies.

Familiarity with physical build EDA tools, including Synopsys and Cadence.

A great teammate who thrives in a collaborative environment.

AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:

Experience in Linux environments.

TCL, Python, shell scripting abilities.

Experience with data collection and analysis

Understanding of the chip and die verification process

This position is open to all candidates.

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8703661

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מודים לך שלקחת חלק בשיפור התוכן שלנו :)

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3 ימים

Senior Design-for-Test Engineer, ATPG

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

Requirements:
What we need to see:

5+ years of hands on DFT/ATPG experience knowledge & technical experience in DFT ASIC Design and in ATPG tools.

Strong programming skills in scripting languages.

BSc. in Electrical Engineering or Computer engineering.

Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility.

Ways to stand out from the crowd:

Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.

Experience in Mentor TestKompress ATPG tool and retargeting flow.

Programming languages: TCL, PRL, Phyton & Unix shell scripts.

Experience with ATE and Silicon bring-up.

This position is open to all candidates.

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8701217

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תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

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לפני 6 שעות

Senior Physical Design Engineer

חברה חסויה

Location: More than one

Be'er Sheva

Tel Aviv-Yafo

Yokne`am

Job Type: Full Time

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
You will be responsible for complex physical design unit designs, ensuring integration within our innovative builds.
We expect you to run, debug, and approve PnR and verification flows across multiple projects, ensuring strict adherence to our high standards.
You will perform physical design implementation, planning and optimization, contributing to the development of our groundbreaking chips.

Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering.
You should have at least 5+ years of hands-on Physical Design 'Place and Route' experience, demonstrating your proven expertise.
A strong background in Physical Design methodology, including Synthesis, Floorplan, CTS and Routing, is necessary.
Sign-off stages experince such as , 'STA', 'PV', 'LEC' and 'EMIR'.
In-depth knowledge of advanced silicon process technologies.
Familiarity with physical build EDA tools, including Synopsys and Cadence.
A great teammate who thrives in a collaborative environment.
AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:
AI prompting experience.
Experience in Linux environments.
TCL, Python, shell scripting abilities.
Experience with data collection and analysis.
Understanding of the chip and die verification process.

This position is open to all candidates.

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8703668

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לפני 10 שעות

Senior Synthesis CAD Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

Join our powerful Networking Silicon engineering team as a Synthesis Senior CAD Engineer! In this pivotal role, you'll be at the forefront of developing the industrys advanced high-speed communication devices, delivering outstanding efficiency and minimal latency. This is your chance to architect, build, and improve advanced RTL to PNR tools, flows and methodologies using the worlds latest process technologies. Be part of a group thats driving technology forward and pushing the frontiers of development.

What you will be doing:

Methodology Deployment: Design and refine sophisticated Synthesis flows to meet ambitious Power, Performance, and Area (PPA) objectives.

Partner closely with upstream Front-End Design and downstream Place & Route (P&R) flows development teams. Define boundaries, resolve design constraints, and bridge systemic execution gaps.

Develop robust and scalable scripts using Tcl/Python to improve Flow Turnaround Time (TAT). Integrate next-generation capabilities such as AI/ML automation into production runs.

Serve as a subject matter expert and trusted representative for adjacent project teams. Provide proactive support, deep-dive debugging of complex tool failures, and formal synthesis training to build teams.

Requirements:
What we need to see:

Academic Background: B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

Core Synthesis Experience: 3+ years of hands-on experience in VLSI synthesis flows, with deep, proven expertise in Synopsys Fusion Compiler or Design Compiler (DC-Top/DC-Ultra).

Technical Skills: Strong proficiency in Tcl or Python scripting within a production-level CAD/EDA environment.

Attitude & Ownership: A highly enthusiastic, dedicated approach with a demonstrated "sense of ownership" to proactively step into process vacuums and drive complex tasks to completion.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Genus/ Innovus/Tempus).

Experience in methodology definition / flow ownership of synthesis / Place and Route/ STA steps is an advantage.

Great teammate with strong ownership, self-learning skills, and the ability to work autonomously.

This position is open to all candidates.

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8703198

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תודה על שיתוף הפעולה

מודים לך שלקחת חלק בשיפור התוכן שלנו :)

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לפני 6 שעות

Senior Chip Design Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

We are looking for an experienced Design Engineer to join the YU design team and develop the next generation technologies.

As a design engineer in the YU design team, you will participate in definition and implementation of our boot and chiplet control technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated boot components into various projects and using state-of-the-art technologies.
As a member of our YU design team, you will participate in defining various boot and chip controller features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

Requirements:
What we need to see:
B.SC./ M.SC. in Computer Engineering/Electrical. Engineering/Communication Engineering.
5+ years of practical experience.
Exposure to rtl implementation and coding.
Familiarity with verification tools.
Strong debugging, problem solving and analytical skills.
Strong communication and social skills are required.
Ability to work in a geographically diverse team environment.
Self motivated, independent and target oriented.
High Level of English.

Ways to stand out from the crowd:
Prior Design or Verification experience.
Experience in developing sophisticated design blocks.
Knowledge in Mixed Signals, Analog, and Behavioral Models for Verification.
Knowledge in Chip boot and Infrastructures.
Experience in working with back-end on area, power and timing closures.

This position is open to all candidates.

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8703701

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מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

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לפני 6 שעות

Senior DFT Design Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

Requirements:
What we need to see:

B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.

5+ years of practical experience.

Exposure to rtl implementation and coding.

Familiarity with verification tools.

Strong debugging, problem solving and analytical skills.

Strong communication and social skills are required.

Ability to work in a geographically diverse team environment.

Self motivated, independent and target oriented.

Ways to stand out from the crowd:

Prior Design or Verification experience.

Experience in developing sophisticated design blocks.

Integration of design elements to large cluster or full-chip.

Experience in working with back-end on area, power and timing closures.

Scripting ability.

This position is open to all candidates.

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8703659

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מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

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לפני 6 שעות

Chip Design Manager

חברה חסויה

Location: Yokne`am

Job Type: Full Time

We are looking for a Chip Design Manager to join our Networking team! As a Chip Design Manager in our Networking Business Unit, you will lead a team of highly skilled engineers responsible for verifying the next generation of our cutting-edge network products and GPU technologies. This is a unique opportunity to make a real impact at the heart of our AI and HPC revolution, while working in a fast-paced, innovative environment. You will join a passionate, experienced team working at the forefront of silicon verification - using advanced methodologies and tools to ensure design correctness for world-class solutions in data centers, high-performance computing, networking, and storage.

What You'll Be Doing:

Lead and grow a team of formal verification engineers focused on pre-silicon FV of complex digital designs.

Define and drive strategies and methodologies across multiple projects to prove design correctness and ensure quality.

Collaborate closely with Architecture, Design, and DV teams to identify verification needs and drive closure.

Provide technical guidance, mentoring, and support to engineers on the team.

Own planning and execution of verification deliverables to ensure high quality and timely tapeouts.

Requirements:
What We Need to See:

BSc or MSc in Electrical/Computer Engineering, Computer Science, or Mathematics.

5+ years of managerial experience leading engineering teams in chip design or verification.

8+ years of industry experience in RTL design, functional verification, or related domains.

Strong understanding of chip design flows and verification methodologies.

Excellent leadership, analytical, problem-solving, and communication skills.

Ways to Stand Out from the Crowd:

Experience with formal verification tools and methodologies (e.g., JasperGold, VC Formal).

Background in assertions, coverage models, or formal testbench development.

Track record of building and scaling high-performing engineering teams.

A passion for recruiting, mentoring, and developing talent.

This position is open to all candidates.

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8703690

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מודים לך שלקחת חלק בשיפור התוכן שלנו :)

המשרה נמחקה

תוכל לצפות בה בדף המשרות שלי

המשרה הוחזרה לרשימת תוצאות החיפוש

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לפני 6 שעות

Senior STA Engineer, Sub-chip

חברה חסויה

Location: More than one

Be'er Sheva

Tel Aviv-Yafo

Yokne`am

Job Type: Full Time

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC level.

Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.

Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.

Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.

AI use for timing optimization and data analysis.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering.

At least 5+ years of hands-on STA experience.

Experience in Prime Time and signoff methodologies.

A great teammate who thrives in a collaborative environment.

AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:

Agentic Frameworks.

AI prompting experience.

Experience in Linux environments.

TCL, Python, shell scripting abilities.

Experience with data collection and analysis.

This position is open to all candidates.

עדכון קורות החיים לפני שליחה

8703665

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