דרושים » חשמל ואלקטרוניקה » Hardware Engineer

Required Post-Silicon Validation Engineer
About The Position
We build cutting-edge radar chipsets for next-generation automotive sensing systems. As a Post-Silicon Validation Engineer, you will play a critical role in bringing complex mixed-signal ICs from silicon to system readiness.
Responsibilities
Perform validation of advanced radar ICs from bring-up through full functional and performance testing
Translate system and chip-level requirements into comprehensive validation plans and test cases
Develop automated test environments using lab instrumentation and custom scripts
Execute silicon bring-up and validate key subsystems (clocking, power, CPU, interfaces, sensors)
Perform electrical and parametric validation, including high-speed, power, and interface testing
Run characterization across PVT conditions and analyze large datasets
Debug complex silicon issues and work closely with design, verification, and system teams
Support device readiness for system integration and productization.

The Senior Hardware Test Engineer is responsible for developing, implementing, and sustaining test processes and equipment used in the manufacturing of hardware products. This role ensures that products meet quality, reliability, and performance standards through robust test strategies, automation, and continuous improvement. The engineer acts as a bridge between design engineering, manufacturing operations, and quality assurance, supporting new product introductions (NPI) through to mass production and sustaining phases.
This is a great opportunity to be part of one of the fastest-growing AI infrastructure companies in history, an organization that is in the center of the hurricane being created by the revolution in artificial intelligence.
we are the data platform company for the AI era. We are building the enterprise software infrastructure to capture, catalog, refine, enrich, and protect massive datasets and make them available for real-time data analysis and AI training and inference. Designed from the ground up to make AI simple to deploy and manage, our company takes the cost and complexity out of deploying enterprise and AI infrastructure across data center, edge, and cloud.
Our success has been built through intense innovation, a customer-first mentality and a team of fearless workers who leverage their skills & experiences to make real market impact. This is an opportunity to be a key contributor at a pivotal time in our companys growth and at a pivotal point in computing history.
Role and Responsibilities:
Test Development & Validation
Design, develop, and implement test plans, test fixtures and infrastructure.
Collaborate with R&D to define test requirements early in the product lifecycle.
Develop test scripts and automation software (Python, LabVIEW, C#, etc.) to improve coverage and efficiency.
Validate test coverage, yield, and reliability through statistical analysis (GR&R, Cpk, SPC).
New Product Introduction (NPI)
Support EVT, DVT, and PVT phases with test readiness and execution.
Lead test process transfer to contract manufacturers (CMs) or ODM partners.
Train CM engineers/technicians on test systems and procedures.
Ensure compliance with safety, regulatory, and customer requirements.
Manufacturing Support & Continuous Improvement
Monitor production test yields, debug failures, and drive root cause analysis (RCA).
Implement corrective actions and continuous improvements to reduce test time, cost, and false failures.
Maintain and calibrate test equipment and fixtures.
Support ECO (Engineering Change Orders) by updating test plans and equipment accordingly.
Cross-Functional Collaboration
Work closely with hardware, firmware, and reliability engineers to improve product testability and robustness.
Partner with Quality and Operations to ensure smooth scaling into mass production.
Engage with suppliers and CM partners on test strategy alignment.

We are looking for a hands-on Hardware Design Engineer to own the full hardware lifecycle - schematic capture, PCB layout, mixed signal circuit design, power architecture, bring-up, and regulatory certification - across current and next-generation hardware.

Responsibilities

Digital Hardware Design - MCU, PHY, Ethernet & PoE

Design the complete digital hardware stack: NXP i.MX RT MCU schematic and BGA layout, Ethernet PHY circuit and controlled-impedance Ethernet routing. Design and validate the IEEE 802.3af PoE front-end : PD handshake, mid/end-span bridge rectifiers, isolated flywheel buck , and optocoupler feedback regulation; analyse cross-domain IO level margins across all MCU interfaces to confirm safe driver/receiver operation.

RF & Analog Circuit Design

Design the ISM transmit chain and 2.4 GHz AoA receive chain; simulate match networks with ADS or equivalent and validate with VNA S-parameter measurements.

PCB Design & Layout

PCB layout: Define stack-up and controlled-impedance rules; route high pin-count BGAs and high-speed peripherals with length tuning; partition RF, digital, and power domains for FCC/ETSI compliance.

Power, calibration & test: Design DCDC/LDO supplies and power distribution; define hardware test procedures for RF power and frequency calibration at production.

Production Support

Failure analysis (field & manufacturing)

Yield improvement

Cost reduction

Post-Silicon Verification Support

Required Chip Test Engineer
About The Position
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

Required Power and Signal Integrity Engineer
About the job
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
Responsibilities
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

Rק/וןרקג Power and Signal Integrity Engineer, PhD Graduate
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
Responsibilities
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Establish design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.
Document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers.

Required Staff Analog Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Analog Design Engineer, you will design and integrate analog sub-systems. You will be responsible for ensuring the analog front-end (AFE) communicates with the digital signal processor (DSP), the package and silicon are a single electrical entity. Your work will bridge the analog and digital worlds to enable industry-leading performance.
The ML, Systems, & Cloud AI (MSCA) organization, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.).
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Own the architecture and implementation of a major sub-component, such as the entire receiver AFE or the clocking/phase-locked loop (PLL) distribution network.
Design the critical suspension system (e.g., equalization/continuous-time linear equalizer (CTLE), analog-to-digital converter (ADC) that allows the digital core to function perfectly despite a noisy, high-loss channel.
Lead the definition and design of test chips to prove out novel topologies and circuit techniques in next-generation gate-all-around (GAA) nodes.
Work with DSP, firmware, and system architects to define hardware/software partitioning and interface specifications.
Provide technical guidance and mentorship to engineers on the team.

Required Senior Board Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of םור direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Hardware Board Design Engineer, you will own the electrical design of complex High Performance Computing (HPC) systems. You will drive the development of next-generation AI accelerator boards, ensuring they meet signal integrity, power delivery, and thermal requirements. You will work cross-functionally with Silicon (ASIC), Signal Integrity, Power, Mechanical, and Manufacturing teams to bring products from concept to mass production.
Responsibilities
Lead the schematic capture and component selection for high-density, multi-layer Printed Circuit Boards (20+ layers) incorporating high-power ASICs (TPUs/CPUs), FPGAs, and high-speed memory (High Bandwidth Memory/DDR5).
Design and validate high-speed interfaces including Peripheral Component Interconnect Express (PCIe) Gen 6.0/7.0, 400G/800G/1.6T ethernet (PAM4). Collaborate with Signal Integrity (SI) engineers to define routing constraints and stack-up.
Design multi-phase power regulators (VRMs) capable of delivering 1000A currents with fast transient response for AI processors.
Work closely with PCB layout designers to guide placement and routing of critical signals and power planes.
Lead the lab bring-up of first-silicon/first-board. Debug complex hardware issues using oscilloscopes, Time-Domain Reflectometers (TDRs), and logic analyzers. Root-cause failures to component, assembly, or design issues.

Required RTL Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. You will develop/define design options for performance, power and area.
Responsibilities
Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog).
Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SoC-level.

Required Senior Post-Silicon Validation Engineer, Networking
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We are building a new team to lead the post-silicon validation efforts for our cutting-edge product. We're looking for highly motivated and talented engineers to join us in ensuring the quality and functionality of our next-generation networking silicon. This is a unique opportunity to be part of a foundational team and make a significant impact.
As a Silicon Validation Engineer, you'll play a pivotal role in the validation of our custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. Your expertise in post-silicon validation will be essential in identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Conduct in-depth analysis into the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities.
Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python or C/C++, running on Pre-Silicon (Pre-Si) emulation platforms and primarily on the silicon.
Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues.
Contribute to the development of test infrastructure and methodologies to improve validation efficiency and coverage.