דרושים » הנדסה » DFT Engineer

we are looking to hire a talented VLSI Design Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips.
If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Bring architecture requirements of AI Chips to a power and area efficient VLSI implementation with the right performance.
Work along with verification to enable a fully functional design.
Work along with backend and DFT to converge the design into silicon.
Join the bring up of the features with SW when silicon is back in lab and the magic happens.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.



Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!



What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

we are looking to hire a talented Verification Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips. If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Collaborate with architecture and design teams to define and implement comprehensive testcases for NN processor and SoC blocks and flows.
Maintain, enhance, and scale the UVM‑based verification environment to support efficient and robust verification.
Own end‑to‑end verification of system flows to ensure the design is fully functional, correct, and meets performance expectations.
Drive root‑cause analysis and debug across RTL, testbench, and system layers to ensure high‑quality design closure.
Define, track, and close functional and performance coverage to guarantee verification completeness.
Continuously improve verification methodologies, automation, and workflows to increase productivity and coverage efficiency.

We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

In this highly-visible role you will assume responsibility over a full range of DFT in an extremely challenging project, leading a talented team of engineers, working closely with frontend and backend teams. You will participate in architecture and design reviews, create design solutions for testability, debug ability, reliability and yield improvement. You will provide design constraints for implementation and sign-off. You will build work plans, drive and track their execution. You will be closely involved in silicon bring-up, reliability testing and advanced physical failure analysis activities, and will be responsible for getting a high-quality product out into AWS fleet for millions of our customers quickly. Come and join us as we work hard, have fun, and make history.

We're looking for a talented SoC Integration Lead to join our Nitro team and help shape what comes next. You will spearhead the SoC integration activities of sophisticated networking chips, collaborating closely with Architecture, RTL Design, Physical Design, Package Design, Verification, Software, DFT, and additional teams in a dynamic, open, and fast-paced environment. As a member of the Nitro project, you will have influence over the device through its entire lifecycle from product definition to mass production. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries.

Key job responsibilities
Take full ownership of SoC integration, including IPs development, partitioning, clock domain crossing (CDC), reset domain crossing (RDC), exploratory synthesis, and design quality verification.
Drive chip-level design implementation by partnering with multiple teams including Architecture, RTL Design, DFT, Verification, System Verification, STA, and Physical Design.
Oversee the creation of SoC-level IP blocks such as fabrics, interfaces, and security modules.
Lead RTL integration activities including micro-architecture definition, RTL coding and debug, synthesis and timing closure, and sign-off.
Address diverse functional and structural challenges, encompassing functional debugging, physical design preparation, emulation, and design quality issue resolution.
Contribute to the creation and implementation of design flows and automated solutions that facilitate efficient SoC development.
Support Verification and Emulation teams through test plan development and coverage review.
Ensure the chip meets quality and reliability standards while delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders.

The Senior Hardware Test Engineer is responsible for developing, implementing, and sustaining test processes and equipment used in the manufacturing of hardware products. This role ensures that products meet quality, reliability, and performance standards through robust test strategies, automation, and continuous improvement. The engineer acts as a bridge between design engineering, manufacturing operations, and quality assurance, supporting new product introductions (NPI) through to mass production and sustaining phases.
This is a great opportunity to be part of one of the fastest-growing AI infrastructure companies in history, an organization that is in the center of the hurricane being created by the revolution in artificial intelligence.
we are the data platform company for the AI era. We are building the enterprise software infrastructure to capture, catalog, refine, enrich, and protect massive datasets and make them available for real-time data analysis and AI training and inference. Designed from the ground up to make AI simple to deploy and manage, our company takes the cost and complexity out of deploying enterprise and AI infrastructure across data center, edge, and cloud.
Our success has been built through intense innovation, a customer-first mentality and a team of fearless workers who leverage their skills & experiences to make real market impact. This is an opportunity to be a key contributor at a pivotal time in our companys growth and at a pivotal point in computing history.
Role and Responsibilities:
Test Development & Validation
Design, develop, and implement test plans, test fixtures and infrastructure.
Collaborate with R&D to define test requirements early in the product lifecycle.
Develop test scripts and automation software (Python, LabVIEW, C#, etc.) to improve coverage and efficiency.
Validate test coverage, yield, and reliability through statistical analysis (GR&R, Cpk, SPC).
New Product Introduction (NPI)
Support EVT, DVT, and PVT phases with test readiness and execution.
Lead test process transfer to contract manufacturers (CMs) or ODM partners.
Train CM engineers/technicians on test systems and procedures.
Ensure compliance with safety, regulatory, and customer requirements.
Manufacturing Support & Continuous Improvement
Monitor production test yields, debug failures, and drive root cause analysis (RCA).
Implement corrective actions and continuous improvements to reduce test time, cost, and false failures.
Maintain and calibrate test equipment and fixtures.
Support ECO (Engineering Change Orders) by updating test plans and equipment accordingly.
Cross-Functional Collaboration
Work closely with hardware, firmware, and reliability engineers to improve product testability and robustness.
Partner with Quality and Operations to ensure smooth scaling into mass production.
Engage with suppliers and CM partners on test strategy alignment.

Required ASIC Design Engineer - Silicon One
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.

We are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities:
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

Join our powerful Networking Silicon engineering team as a Synthesis Senior CAD Engineer! In this pivotal role, you'll be at the forefront of developing the industrys advanced high-speed communication devices, delivering outstanding efficiency and minimal latency. This is your chance to architect, build, and improve advanced RTL to PNR tools, flows and methodologies using the worlds latest process technologies. Be part of a group thats driving technology forward and pushing the frontiers of development.

What you will be doing:

Methodology Deployment: Design and refine sophisticated Synthesis flows to meet ambitious Power, Performance, and Area (PPA) objectives.

Partner closely with upstream Front-End Design and downstream Place & Route (P&R) flows development teams. Define boundaries, resolve design constraints, and bridge systemic execution gaps.

Develop robust and scalable scripts using Tcl/Python to improve Flow Turnaround Time (TAT). Integrate next-generation capabilities such as AI/ML automation into production runs.

Serve as a subject matter expert and trusted representative for adjacent project teams. Provide proactive support, deep-dive debugging of complex tool failures, and formal synthesis training to build teams.