דרושים » חומרה » Hardware Team Lead

Were looking for a talented Hardware Engineer to join our innovative team.
Responsibilities:
Design, develop, and validate hardware boards for advanced radar and chip-based systems, with a strong focus on digital circuitry and power supply design.
Perform hands-on lab work (HO), including board bring-up, debugging, troubleshooting, repair, and continuous improvement of existing hardware.
Define, write, and execute comprehensive test plans and test setups for board-level validation.
Analyze test results, characterize performance, and document findings, including detailed test reports, failure analysis, and corrective actions.
Support schematic design activities and contribute to the development and maintenance of design environments and databases for EDA tools.
Experience with SI/PI simulation tools.
Collaborate closely with lab technicians, engineers, and cross-functional teams to ensure efficient execution of lab activities and project goals.
Take an active role in prioritizing tasks, driving technical decisions, and owning deliverables end-to-end.

we are looking for a Chip Test Engineer.
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a design team manager within the server chip design team, you will use your asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.in this role, you will oversee the intellectual property (ip) and SOC vlsi design cycle from architecture to production. you will own and manage ip, subsystems and SOC development, leading a group of designers and design tech leads. you will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our cloud, global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead design activities at ips, subsystems, and system -on-chips (socs).
plan, execute, track progress, assure quality, and report status of the assigned activity.
work closely with internal customers and support multiple activities and deliverables.
assure and manage deliverables quality at all rtl design categories including reviews, static checks, design for physical design, power, etc.

we are looking for an excellent virtual platform fw engineer to join the infrastructure and simulation integration group. in this role, you will integrate a systemc/tlm virtual hardware platform (delivered by the hardware modeling team) with firmware, make the end to end flow run reliably, and turn it into a productive environment for early development and regressions. with many hardworking engineers around the globe, the work environment is complex, driven by a passion for achieving goals, and fast paced. you will learn how large scale firmware projects are operated, maintained, qualified and released, and how firmware and pre-silicon platforms are developed together to accelerate product readiness.
what you will be doing:
work closely with firmware, hardware architecture, systemc modeling, and build/tools teams.
integrate firmware images with a systemc/tlm virtual platform and enable end to end boot, bringup, and feature flows.
define and implement hw-fw interfaces for the virtual platform (mmio, interrupts, dma, boot flows, configuration).
integrate the virtual platform flow into ci, regressions, and nightly qualification, including triage and failure analysis.
drive stability, scalability, and performance of virtual platform runs and regressions.
document processes, guidelines, and tooling that make the virtual platform easy to adopt across teams.

Founded in Tel Aviv in 2016, UVeye is a computer vision and data company that creates automatic vehicle inspection systems to encourage road safety and increase transparency across the automotive industry. With key partnerships including General Motors, Volvo, and CarMax among others, our technology is utilized in manufacturing plants, dealerships, wholesale auctions, delivery fleets, security checkpoints, and more.
With over $380M in funding and strategic partnerships with industry giants such as Toyota, Amazon, General Motors, Volvo, and Hertz, our technology is utilized in manufacturing plants, dealerships, wholesale auctions, delivery fleets, security checkpoints, and more. Our growing global team of over 250 employees is committed to creating a workplace that celebrates diversity, encourages teamwork, and strives for excellence.
UVeye is looking for an experienced Electronics Engineer to join our growing R&D Hardware team and lead and deliver Hardware projects.
Here’s what you’ll be doing:
* Develop and own all electrical modules for UVeye products.
* Integrate new components and sensors into the system.
* Perform PCB development activities for new and improving the existing.
* Lead troubleshoots of faulty electrical components.
* Cooperate with the system engineer, mechanics, and SW teams to develop next-gen features and products.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer pcbs (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (hbm/ddr5).
design and validate high-speed interfaces including pcie gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering >1000a currents with fast transient response for ai processors.
work with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board by debugging hardware issues using oscilloscopes, tdrs, and logic analyzers to root-cause failures to component, assembly, or design issues.

we are now looking for an arch simulation manager to join our nvidia networking team! as a switch-arch simulation manager in nvidias networking business unit, you will lead a team of highly skilled hardware engineers responsible for verifying the next generation of nvidias cutting-edge switch products. this is a unique opportunity to make a real impact at the heart of nvidias ai and hpc revolution, while working in a fast-paced, innovative environment. you will be part of a passionate and experienced team using modern approaches to validate the performance requirements for the next generation of nvidia networking products. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of hardware Verification engineers focused on arch performance validation of complex digital designs.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of simulation deliverables to ensure high quality and timely tapeouts.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a SOC physical design engineer, you will collaborate with functional design, design for testing (dft), architecture, and packaging engineers. additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.the ai and infrastructure team is redefining whats possible. we empower customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our  users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
define and drive the implementation of physical design methodologies.
take ownership of one or more physical design partitions or top level.
drive to the closure of timing and power consumption of the design.
contribute to design methodology, libraries, and code review.
define the physical design related rule sets for the functional design engineers.