דרושים » הנדסה » Tech Lead UAV & Airborne Systems (6355)

A leading technology company in the unmanned aerial systems domain is seeking a Senior Systems Engineer to lead the end-to-end development of complex UAV platforms.

This role carries full system -level responsibility for a multi-disciplinary airborne platform, integrating engineering design, system architecture, performance optimization, and program execution.
Key Responsibilities:
Full system ownership of UAV platforms across the entire lifecycle.
Lead the design and integration of complex systems including airframe, system architecture, propulsion, energy, communications, navigation, and control.
Analyze system requirements and translate them into subsystem-level engineering requirements.
Drive system -level design processes and long-term technical decision-making.
Coordinate and synchronize multiple engineering disciplines (mechanical, electrical, software, etc.).
Lead system integration, testing, and validation activities.
Ensure delivery against quality, schedule, and cost targets.
Work in a matrix environment, influencing cross-functional teams without direct authority.
Contribute to defining technology roadmap and future platform capabilities.

Required Field Application Engineer - AI Accelerators
In this position:
You will serve as the primary technical interface between us and our customers for our AI accelerator product line and future accelerator platforms. You will support customers through the full product lifecycle - from pre-sale technical engagement and proof-of-concept development through production deployment and ongoing field support. You will work hand-in-hand with R&D to investigate and resolve complex issues, develop reference applications and demos, and act as a trusted technical advisor to both customers and internal teams.
Responsibilities
Develop a comprehensive understanding of each customers use case, system architecture, and integration requirements, serving as their primary technical point of contact for all accelerator-related topics.
Provide deep technical support across the accelerator portfolio, including the Dataflow Compiler, model compilation, and runtime integration.
Reproduce, investigate, and drive resolution of complex hardware and software issues in close collaboration with R&D, spanning PCIe integration, driver-level debugging, inference pipeline optimization, and power management.
Lead technical alignment with customers - clearly communicating issue status, setting expectations, coordinating across internal teams, and ensuring customer satisfaction.
Design and implement customer-facing demo and reference applications in C/C++, showcasing accelerator capabilities at major industry events such as CES and other trade shows.
Support pre-sale technical activities including solution scoping, feasibility assessments, and technical presentations to prospective customers.
Provide knowledge transfer and technical enablement to FAEs and partners to scale field support effectiveness.
Collaborate closely with R&D, Product, and Business teams to translate customer needs into actionable product requirements and roadmap input.

We are looking for a dynamic and skilled System Engineer to be a key player in building and optimizing our systems. In this role, youll work on groundbreaking end-to-end solutions, from embedded devices to scalable cloud platforms, with a focus on system integration and performance optimization.
This is a unique opportunity to grow your skills, collaborate with experts, and contribute to the development of technologies that make a real-world impact. If youre excited about pushing the boundaries of whats possible and solving technical challenges at scale, we want to hear from you!
Responsibilities:
Innovative System Design and Seamless Integration
o Lead the design, development, and continuous enhancement of robust, end-to-end system solutions, from embedded hardware to scalable cloud platforms.
o Drive the integration of diverse system components, ensuring smooth communication and optimized performance across all layers of the stack.
Coding for High-Impact Systems
o Use your Python expertise to build scalable and efficient solutions that power critical system features.
o Work closely with cross-functional software development teams to bring new system-level capabilities to life and troubleshoot issues across the stack.
System Optimization and Cutting-Edge Troubleshooting
o Continuously analyze and optimize system performance, ensuring both embedded and cloud-based components run with maximum efficiency and reliability.
o Leverage your troubleshooting skills to diagnose and resolve complex system-level issues, keeping critical services running smoothly.

As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in our company, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. We provide a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of us, is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

We are looking for exceptional senior chip architects to join a world-class team that is reinventing how workloads run at scale.

As a Chip Architect, you will define architecture and micro-architecture across the complete product lifecycle - from initial requirements and early-stage technology exploration through design, implementation, and production deployment. You will explore and analyze architectural options for current and next-generation solutions, including new physical layer (PHY) and interconnect technologies, innovative protocols, and fundamental improvements to our hardware and software stack to make us the best place to run ML workloads and establish Annapurna Labs solutions as the industry-leading platform for Training and Inference workloads.

This role requires a top-down understanding of our complete solution stack, including system architecture, software stack, chip architecture, and microarchitecture. You will work in close collaboration with multiple groups - Software, Silicon engineering, System and Platform teams, and cross-functional teams across us. Your architectural decisions will influence the design of chips deployed on millions of servers worldwide, powering the future of AI, machine learning, and general-purpose compute. This is an opportunity to have large-scale impact on how the world builds and deploys infrastructure.

we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.

we are looking for an experienced Product Line Manager (PLM) for the IoT portfolio to lead product-line planning and execution across the full lifecycle of IoT solutions. This role will own roadmap definition, market and customer requirement analysis, product specification, launch readiness, and ongoing business growth for a portfolio that includes IoT gateways, cellular routers, industrial switches, and related services and platforms. The role works cross-functionally with R&D, solution management, business development, sales, marketing, operations, global services, and partners and OEMs to turn IoT value proposition into market wins.
Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.
Responsibilities
Own the IoT product line lifecycle from strategic planning through execution, launch, and lifecycle management.
Define and maintain the portfolio roadmap, balancing short-term customer needs with long-term strategic priorities.
Translate market needs, customer use cases, and competitive input into product requirements, business cases, pricing and COGS targets, and time-to-market plans.
Lead PLM-owned stages in the feature and release lifecycle, including feature requests, high-level business case creation, GTM readiness, and go / no-go decisions.
Define product functionality through technical specifications and use cases, and work closely with R&D to ensure high-quality end-to-end delivery.
Drive commercialization of IoT portfolio, including offers around secure and resilient SCADA transport, smart IoT solutions, and industrial and utility connectivity use cases.
Work with marketing and product marketing on positioning, launches, presentations, data sheets, webinars, GTM toolkits, and sales enablement content.
Partner with sales and account teams to support customer opportunities, RFIs / RFPs, partner discussions, and strategic deals.
Manage and prioritize initiatives tied to IoT differentiation, including security-by-design, certifications, protocol conversion, edge intelligence, and resilient communications.
Monitor market trends, competitor activity, and adjacent technologies such as private LTE / 5G, edge computing, AI / ML integration, and industrial IoT applications to shape roadmap decisions.
Where relevant, manage partners and OEM relationships, including specifications, commercial alignment, customizations, and sales support.

Required Staff Architect, Digital Signal Processing, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Engineer on the Digital Signal Processing team, you will be a technical leader responsible for architecting and developing the core algorithms that power our next-generation data center interconnects. You will leverage your expertise in communication theory, forward error correction (FEC), and modulation to design novel, low-complexity solutions that push the boundaries of speed and reliability.
This is an executive role where you will not only define the technical direction for critical projects but also mentor other engineers and collaborate across hardware and software teams to bring your goal to life in silicon.
Responsibilities
Lead the architecture, design, and implementation of digital signal processing (DSP) algorithms for high-speed optical communication systems. Drive the long-term technical roadmap for our signal processing and communication architectures by staying current with academic and industry trends.
Develop and analyze novel forward error correction (FEC) and modulation schemes to optimize for performance, power, and complexity tradeoffs.
Create comprehensive system-level models using tools like Matlab, Python, or C++ to simulate and validate algorithm performance.
Collaborate closely with logic design, verification, and software teams to ensure the successful implementation, integration, and bring-up of algorithms in custom silicon.
Provide technical leadership and mentorship to a team of DSP and communication systems engineers, fostering innovation and engineering excellence.

Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Cloud customers, and billions of users worldwide.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Required Staff Analog Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Analog Design Engineer, you will design and integrate analog sub-systems. You will be responsible for ensuring the analog front-end (AFE) communicates with the digital signal processor (DSP), the package and silicon are a single electrical entity. Your work will bridge the analog and digital worlds to enable industry-leading performance.
The ML, Systems, & Cloud AI (MSCA) organization, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.).
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Own the architecture and implementation of a major sub-component, such as the entire receiver AFE or the clocking/phase-locked loop (PLL) distribution network.
Design the critical suspension system (e.g., equalization/continuous-time linear equalizer (CTLE), analog-to-digital converter (ADC) that allows the digital core to function perfectly despite a noisy, high-loss channel.
Lead the definition and design of test chips to prove out novel topologies and circuit techniques in next-generation gate-all-around (GAA) nodes.
Work with DSP, firmware, and system architects to define hardware/software partitioning and interface specifications.
Provide technical guidance and mentorship to engineers on the team.