דרושים » חשמל ואלקטרוניקה » FPGA Engineer (6294)

FPGA Verification engineer (6160) We are seeking a talented and experienced FPGA Verification engineer to join our hardware development team. In this role, you will be responsible for defining and executing comprehensive verification strategies for complex FPGA-based systems, from architectural definition through system integration.

We are seeking a System HW Engineer to define, shape, and integrate solutions for the next generation of our cloud platforms.

As a System Engineer on the hardware team, you will define systems for our Labs' Network Interface Card (NIC) hardware, support the development and validation of our NIC, and help bring the NIC to mass production.
You'll lead the implementation of new hardware interface technologies and scale them to large-scale deployment, continuously delivering a world-class customer experience. This fast-paced, intellectually challenging position requires collaboration with technical experts, senior leaders, and multiple technology teams.


Key job responsibilities
Define and design systems to support K2 cards development and manufacturing.
Define and provide feedback to the design of the K2 Smart Network Interface Card.
Work with design partners and manufacturing sites, to enable healthy mass production of the K2 card.
Analyze and debug design/manufacturing/integration issues.
Continuously assess process capabilities and innovate to simplify processes, reduce costs, and shorten the time cycle of K2 cards development and manufacturing.
Collaborate with members of cross-functional teams, to gain knowledge and improve product design, processes, and quality.
Work with customers, to optimize the entire value stream and put together joint processes that will lead to improved time cycle and lower costs.
Willing to travel abroad one or two times a year, for a week at a time.

Required Staff Analog Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Analog Design Engineer, you will design and integrate analog sub-systems. You will be responsible for ensuring the analog front-end (AFE) communicates with the digital signal processor (DSP), the package and silicon are a single electrical entity. Your work will bridge the analog and digital worlds to enable industry-leading performance.
The ML, Systems, & Cloud AI (MSCA) organization, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.).
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Own the architecture and implementation of a major sub-component, such as the entire receiver AFE or the clocking/phase-locked loop (PLL) distribution network.
Design the critical suspension system (e.g., equalization/continuous-time linear equalizer (CTLE), analog-to-digital converter (ADC) that allows the digital core to function perfectly despite a noisy, high-loss channel.
Lead the definition and design of test chips to prove out novel topologies and circuit techniques in next-generation gate-all-around (GAA) nodes.
Work with DSP, firmware, and system architects to define hardware/software partitioning and interface specifications.
Provide technical guidance and mentorship to engineers on the team.

Job Description:
Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Modeling of HW specification of new architecture and microarchitecture. Working closely with architect and microarchitecture on modeling the specification.