we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

As the leader of the team, you will be responsible for delivering a state-of-the-art functional simulator for the family of routing and switching devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:

Lead and mentor and scale the team to 7-10 engineers, fostering a collaborative and inclusive environment
Oversee the design and delivery of a high-performance, reliable, and user-friendly behavioral model for devices
Collaborate closely with cross-functional teams including ASIC Architecture, Software, and Hardware to align goals and ensure seamless execution
Champion engineering excellence by modeling hands-on problem solving and debugging best practices
Guide team members in their professional development with tailored growth plans and regular feedback

we are now looking for a chip design Verification engineer to join the chip design methodologies team. the team is in charge of the verification methodologies, shared code, training, and embracing new technologies. one of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. this position offers the opportunity to have real impact in a dynamic, technology-focused company.
what you'll be doing:
develop shared verification code and solutions to be widely used by the chip design team.
develop groundbreaking methodologies to create a flawless experience for Verification engineers to keep the focus on new problems.
collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our verification process.
understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
collaborate with designers, verification specialists to accomplish your tasks.
develop training sessions.

we are looking for a Senior Design Engineer who wants to push boundaries, work hard, and help build something that has never been done before.

The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.

Your Day to Day
Own the design, micro-architecture, and implementation of digital logic for a high-performance ASIC
Translate system-level requirements into detailed micro-architecture and RTL designs
Develop high-quality RTL code in Verilog/SystemVerilog
Work closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionality
Participate in design reviews, propose improvements, and ensure compliance with coding and design guidelines
Integrate and debug digital modules in simulation and lab environments
Support synthesis, timing closure, performance optimization, and power reduction activities
Collaborate with verification teams to define test plans and ensure thorough coverage
Contribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the mission

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
work in a combined design and verification team which develops core units within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, full-chip, fw and post-silicon validation.
your daily work will involve all aspects of design verification: planning, coding, coverage and integration

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join tel-aviv/beer-sheva group, working on verification in the field of encryption accelerators.
verification of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve verification and might involve any or all aspects of chip development including micro-architecture.
work closely with firmware and other groups around the globe.
work mode: hybrid home-office.

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
 
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will use application-specific integrated circuit (asic) design experience to be part of a team that develops complex asic system -on-chip ( SOC ) intellectual property from proof-of-concept to production. this includes creating ip level microarchitecture definitions, register-transfer level (rtl) coding and all rtl quality checks. you will also have the opportunity to contribute to design flow and methodologies, including design generation automation. you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. you will develop/define design options for performance, power and area.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and cloud. our end users are, cloud customers and the billions of people who use services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the ip microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
perform rtl development (coding and debug in verilog, systemverilog).
conduct function/performance simulation debug and lint/cdc/fv/upf checks.
engage in synthesis, timing/power closure, and asic silicon bring-up.
contribute to verification TEST plan and coverage analysis of block and SOC -level.

* Manage and build a world class team managing ASIC design, micro-arch, SDC constraints and integration efforts of the project.
* Translate high level goals to measurable plans and milestones. Lead RTL design, quality checks, and manage schedule for on-time delivery of key IPs.
* Work with verification and physical design teams to achieve high quality design.
* Interface with IP teams and manage schedule and delivery of IPs for successful TO.
* Guide and mentor junior engineers as required.
* Hire and retain tier one engineers and foster teamwork with cross functional collaboration.
* Build a culture of execution excellence coupled with innovation.
* Build a team of hard-working and passionate leaders as we scale.
* Maintain close interactions with NPI, Packaging, DFT, Architecture teams.
* Own power, performance and area optimization of design.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. we make outstanding artificial intelligence happen and accelerate open-ais chat-gpt, for example. we believe in our people and products and seek excellent people to join us!
we're looking for a hardware u/architect for our switch division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both ethernet and infiniband. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system requirement and help define the por of our switch product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand ethernet, infiniband and nvlink protocols.