we are looking for a dedicated SOC clocks design automation engineer to join our networking silicon team. in this role, youll focus on developing and supporting clock-related design flows and methodologies for SOC and networking chips, ensuring efficient and high-quality design implementation. youll also chip in to SOC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. introduction
what you'll be doing:
develop and maintain design automation and methodologies for SOC and networking clock flows.
collaborate with design, sta, and project teams to ensure timely and high-quality design closure.
develop and improve SOC top-level automation scripts and flows built upon existing infrastructure and tools.
support SOC integration and construction flow activities across multiple projects.
assist in timing, power, and noise analysis to ensure efficient performance.

we are now looking for a versatile, fast learner, and highly motivated fe integration and eda tools engineer! as a member of our switch organization, you will be part of frontend integration and eda flows for a highperformance, lowpower switch chip. our fei team drives methodologies, automation, and quality for our frontend implementation and cd/ci, working closely with architecture, design, verification, and backend teams. this position offers you the opportunity to have real impact in a dynamic, technologyfocused company influencing future switch product lines. 
what you'll be doing:
driving frontend integration of major blocks in a pioneering ethernet switch asic, from rtl handoff through synthesis and signoff checks.
building, maintaining, and improving eda flows and methodologies for the switch org (lint, cdc/rdc, formal, synthesis/uls, fedct/fefc and related frontend signoff flows).
working closely with logic design and microarchitecture teams to define integration constraints, clocks/resets, interfaces, and quality targets.
partnering with dv, be, and cad/flow teams to ensure robust, scalable, and efficient frontend implementation across the project.
developing automation and infrastructure (scripts, regression flows, dashboards) to improve productivity, and debuggability.
debugging complex tool, flow, and design issues; driving rootcause analysis and longterm methodology improvements.

At Lumissil, we are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, Lumissil is the place to develop your skills, innovate, and grow your career. Why join us?
* Work on cutting-edge automotive projects
* Learn from a talented and supportive team
* Gain exposure to real-world automotive challenges
* Grow your career in a collaborative and inspiring environment If you’re ready to take the next step in your career and be part of something meaningful, we’d love to meet you! About The Position: As a Junior ASIC Design Engineer at Lumissil, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where you’ll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions
* Support and learn from real emulation platforms used in production-grade designs
* Contribute to RTL implementation and gain practical experience in design flows
* Assist with verification and backend (BE) activities, learning industry best practices
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in our company, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. We provide a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of us, is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip ( SOC ) group is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams. 
what you'll be doing:
lead the end-to-end execution, tracking, and convergence of chip-level cdc and rdc for complex socs across all ips and partitions.
plan and orchestrate cdc/rdc signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.
run and maintain cdc/rdc flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.
triage violations efficiently: root-cause to rtl, constraints, tool setup, or ip models; prioritize and drive fixes to closure with owners.
verify reset architecture and rdc robustness (reset domain intent, release sequencing, glitch detection, fanout).
author and review cdc/rdc constraints, waivers, and justifications; ensure auditability and signoff quality.
automate runs, report parsing, dashboards, and kpis for closure tracking using scripting and data tooling.
partner with rtl, dv, dft, sta, pd, and architecture to align fixes, manage ecos, and protect cdc/rdc quality during late design changes.
define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.
continually improve methodology and training to prevent recurring cdc/rdc issues and accelerate convergence.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.