דרושים » תוכנה » Verification engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.

We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.
Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Verification Engineer, you will work as part of a research and development team, and will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.

As an SOC Verification Engineer, you will verify the design and implementation of our SOC technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches and NIC SoC product lines. We are working closely with a wide range of aspects - chip design, DFT, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our SOC solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for verification of the clock design elements, architecture and micro-architecture using sophisticated verification methodologies.

As a member of our SOC verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

our EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.

Responsibilities:
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches.
Work closely with the verification team to ensure the quality of the product.
Build and maintain a smart and scalable verification environment that ties into various systems.
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.

As an RTL Verification Engineer, you will be responsible for complex logical units of a new, cutting-edge RISC‑V application processor, working closely with architecture, design, modeling, software, validation, and implementation teams to meet all functional requirements, including performance, power, and area (PPA) goals.
An ideal candidate will have at least 3 years of experience in one or more of the following: CPU, RISC‑V architecture, micro‑controllers, and memory or cache controller design verification.
This is a 5 days onsite position in Hod Hasharon
Responsibilities
Understand high-level specifications and detailed requirements for application processor design logical units.
Verification from plan to execution, build and own all functional verification stages of a unit within application processor.
Collaborate with cross functional teams such as architecture, design, and software teams on test plan development.
Deliver on time with tight schedule entire verification suite including full functional and code coverage closure before tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer in our Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.