Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Looking for a CPU Architect with expertise in HW/SW codesign of dense computational logic (e.g., vector, matrix)
The role includes but is not limited to:
Analysis of technical challenges in relevant use cases and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions in cooperation with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts.
(Preferably) models CPU functionality, performance and power in simulators.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

We are currently looking for a Performance Simulation Expert develop and evaluate next generation performance features as well as develop the future generation of our Compute system simulation infrastructure, models and analysis tools
Responsibilities:
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

With the explosive growth of AI technologies and the Internet industry, data centers have become digital hubs and infrastructures of the Internet industry in the digital economy era. Computing networks, as core components of data centers, have features such as topology, scalability, throughput, reliability, and latency that directly affect data center functionality and performance. The computing cluster networking lab explores architecture and technological innovation for meeting the challenges of future large-scale AI & HPC data centers. .. The labs mission is to lead our company to achieve differentiated competitiveness in high-performance computing cluster network infrastructure, and to support Huawei's industry-leading computing cluster.
Position Overview
In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture. As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.
Responsibilities
You will perform a wide range of duties including:
Architecture Innovation:
Deeply analyzing the advantages and disadvantages of mainstream network systems, to find opportunities for network architecture innovation;
Insight into the technology developing trend of the high-performance computing network field, and leading the corresponding technology planning.
Exploring new architectures of high-performance computing network systems and efficiently integrating communication library, topology, and network protocol to solve performance bottlenecks.
Technical breakthroughs in networking and cluster routing algorithm：
Analyzes computing cluster network performance and leads the development of computing cluster network technologies
Research and optimize the heterogeneous interconnection topology of key computing chips to continuously improve the key competitiveness of Huawei computing heterogeneous chipsets
Responsible for the research of data center network technologies, and guide network topology design and routing algorithm development
Group leadership:
Lead the development of a comprehensive system architecture for AI Fabric and HPC Fabric solutions
Manage and mentor highly skilled team leaders, to ensure that the group operates together in pursuit of common goal
Foster a collaborative and innovative work environment
Provide technical guidance and support to team members
Collaborate closely with cross-functional teams internationally, including hardware,
software, and ucode design teams, to ensure alignment of architectural decisions with
product and platform common objectives
Initiate and supervise collaborations with top academic researchers in Israel and abroad
Stay up to date with emerging technologies and industry trends in AI, HPC and big data industries
Evaluate and recommend technologies and next generation projects
Occasional travel related to ongoing projects, seminars, conferences etc.

in this role, youll work to shape the future of ai/ml hardware acceleration. you will have an opportunity to drive tpu (tensor processing unit) technology that powers our most demanding ai/ml applications. youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our tpu. you'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on tpu architecture and its integration within ai/ml-driven systems.
our silicon team is driving the future of cloud data center computing. as a system on chip input output ( SOC io) architect, you will help define a new generation of our products. you will have pivotal responsibilities and serve as the organization mobile industry processor interface (mipi) focal point.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include, cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our cloud, global networking, data center operations, systems research, and much more.
responsibilities
evaluate different silicon solutions for executing mipi and other io peripheries: off-the-shelf components, vendor co-developments and custom designs.
drive vendor execution in various engagements: standard component, build to specification, and co-developments.
collaborate closely with software, design, verification, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
create high performance hardware/software interfaces.
collaborate in developing a new SOC.

As a Principal/ Senior Principal ASIC Architect, you will be the blueprint creator for the future of AI infrastructure. You won't just follow specifications-you will lead the definition and execution of next-generation ASIC solutions targeting hyperscale data centers. From analyzing market requirements to guiding products through their entire lifecycle, your influence will be etched into the silicon that enables the next era of scale-up and scale-out connectivity. If you thrive on solving complex, unnamed challenges and want to shape the architectural foundation of AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Architectural Definition & Strategy

Lead the architectural definition of next-generation ASICs, translating complex market requirements into elegant, high-performance hardware specifications
Drive technical decision-making that balances power, performance, area, and cost (PPAC) to maintain competitive edge in the hyperscale ecosystem
Leverage deep domain expertise to integrate industry standards (Ethernet, UALink, PCIe) into cohesive systems solving demanding AI infrastructure challenges
Product Lifecycle Ownership

Own the architectural journey from initial concept through design, implementation, tapeout, and mass production
Ensure final products deliver on performance promises and meet hyperscaler requirements
Drive architectural exploration and performance modeling to validate design decisions
Technical Leadership & Cross-Functional Collaboration

Act as the technical North Star for the engineering organization in Israel
Collaborate across Architecture, Design, Verification, DFT, and Backend teams to ensure seamless execution
Influence and align cross-functional teams around unified technical vision through strong communication and leadership

Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities
Lead next generation inference solution optimized for power, performance and area. Considering scalable solution for large scale systems with many resources. Covering efficient data delivery and workload map.

We are looking for an experienced System Architect to lead the architecture and technical design of our platform.
In this role, you will define scalable system architecture for AI-driven data platforms, working closely with product management, engineering teams, and customer-facing teams. You will guide technical decisions, ensure architecture consistency across teams, and support successful delivery of our solutions.
The role also includes customer-facing technical engagement, supporting pre-sales activities and providing architectural guidance during complex enterprise deployments.
Responsibilities:
Define and maintain the overall architecture of our platform and solutions
Design scalable distributed systems for large-scale financial data processing
Collaborate with product management and engineering teams to translate product requirements into architecture
Guide development teams on architecture decisions, scalability, and performance
Support pre-sales engagements and customer implementations with technical expertise
Design cloud-native architectures for SaaS and on-premise deployments
Guide architecture of AI-driven analytics and data processing platforms
Promote architectural best practices across teams.