דרושים » הנדסה » Execution Architect

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

We are currently looking for a Performance Simulation Expert develop and evaluate next generation performance features as well as develop the future generation of our Compute system simulation infrastructure, models and analysis tools
Responsibilities:
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

With the explosive growth of AI technologies and the Internet industry, data centers have become digital hubs and infrastructures of the Internet industry in the digital economy era. Computing networks, as core components of data centers, have features such as topology, scalability, throughput, reliability, and latency that directly affect data center functionality and performance. The computing cluster networking lab explores architecture and technological innovation for meeting the challenges of future large-scale AI & HPC data centers. .. The labs mission is to lead our company to achieve differentiated competitiveness in high-performance computing cluster network infrastructure, and to support Huawei's industry-leading computing cluster.
Position Overview
In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture. As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.
Responsibilities
You will perform a wide range of duties including:
Architecture Innovation:
Deeply analyzing the advantages and disadvantages of mainstream network systems, to find opportunities for network architecture innovation;
Insight into the technology developing trend of the high-performance computing network field, and leading the corresponding technology planning.
Exploring new architectures of high-performance computing network systems and efficiently integrating communication library, topology, and network protocol to solve performance bottlenecks.
Technical breakthroughs in networking and cluster routing algorithm：
Analyzes computing cluster network performance and leads the development of computing cluster network technologies
Research and optimize the heterogeneous interconnection topology of key computing chips to continuously improve the key competitiveness of Huawei computing heterogeneous chipsets
Responsible for the research of data center network technologies, and guide network topology design and routing algorithm development
Group leadership:
Lead the development of a comprehensive system architecture for AI Fabric and HPC Fabric solutions
Manage and mentor highly skilled team leaders, to ensure that the group operates together in pursuit of common goal
Foster a collaborative and innovative work environment
Provide technical guidance and support to team members
Collaborate closely with cross-functional teams internationally, including hardware,
software, and ucode design teams, to ensure alignment of architectural decisions with
product and platform common objectives
Initiate and supervise collaborations with top academic researchers in Israel and abroad
Stay up to date with emerging technologies and industry trends in AI, HPC and big data industries
Evaluate and recommend technologies and next generation projects
Occasional travel related to ongoing projects, seminars, conferences etc.

Were looking for an experienced SW Team Manager to join our Simulators Team, where you'll lead the design and development of our hardware simulators - functional and performance models that serve as the source of truth, drive architectural exploration and compiler optimization.
Our simulators model diverse cores within a cutting-edge SoC designed to accelerate Big Data and Database Analytics.
You will collaborate closely with hardware and software teams, contributing to co-design efforts that influence architecture, tooling, and system-level behaviour.

our company, Huaweis Tel Aviv Research and Innovation Center, is looking for an experienced hands-on software engineer and compiler technology expert to join our Future-Computing-Infrastructure expert group. The group designs and develops technologies for the next-generation data center aimed at accelerating AI workloads for a unique HW, optimizing compute resource utilization and reducing data-center costs. Our projects involve hardware and software architecture co-design. They require high-level system understanding, creativity and innovative thinking.
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!
What will you be doing?
Complex static code analysis to determine possible bottlenecks and time-consuming operations within the code of AI model for inference
Architecture, design and implementation of compilation passes, compiling high-level languages to a unique HW
Take initiative to solve technical and business problems
Collaborate with other development and product teams in our company and in China to ensure the successful implementation and delivery of a solution.

As an ML Software Engineer with a focus on low-level and CUDA-based optimizations, you will play a key role in shaping the design, performance, and scalability of machine learning inference systems. Youll work on deeply technical challenges at the intersection of GPU acceleration, systems architecture, and ML deployment.
Your expertise in CUDA, C/C++, and performance tuning will be crucial in enhancing runtime efficiency across heterogeneous computing environments. Youll collaborate with designers, researchers, and backend engineers to build production-grade ML pipelines that are optimized for latency, throughput, and memory use, contributing directly to the infrastructure powering next-generation AI products.This role is ideal for an engineer with strong systems-level thinking, deep familiarity with GPU internals, and a passion for pushing the boundaries of performance and efficiency in machine learning infrastructure.

Responsibilities
Design and implement highly optimized GPU-accelerated ML inference systems using CUDA and low-level parallelism techniques
Optimize memory, compute, and data flow to meet real-time or high-throughput constraints
Improve the performance, reliability, and observability of our inference backend across diverse compute targets (CPU/GPU)
Collaborate with cross-functional teams (including researchers, developers, and designers) to deliver efficient and scalable inference solutions
Contribute to ComfyUI and internal infrastructure to improve the usability and performance of model execution flows
Investigate performance bottlenecks at all levels of the stack-from Python to kernel-level execution
Navigate and enhance a large, complex, production-grade codebase
Drive innovation in low-level system design to support future ML workloads

we are looking for a software integration team lead to join our av group and lead sw deployment and integration for next-generation av platforms. what will your job look like?
lead a team of software integrators responsible for deployment & integration of dedicated sw & hw toward av validation campaigns.
serve as the focal point for platform sw technical challenges in the areas of Embedded sw, Linux, logging platforms, and hw/sw integration toward validation.
drive technical direction, task prioritization, execution planning, and delivery of integration milestones.
collaborate closely with internal & external engineering and validation teams to resolve complex multidisciplinary technical issues, while mentoring and developing team members.
act as an integral part of the platform development leadership in a dynamic, solution-oriented environment.

in this role, youll work to shape the future of ai/ml hardware acceleration. you will have an opportunity to drive tpu (tensor processing unit) technology that powers our most demanding ai/ml applications. youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our tpu. you'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on tpu architecture and its integration within ai/ml-driven systems.
our silicon team is driving the future of cloud data center computing. as a system on chip input output ( SOC io) architect, you will help define a new generation of our products. you will have pivotal responsibilities and serve as the organization mobile industry processor interface (mipi) focal point.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include, cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our cloud, global networking, data center operations, systems research, and much more.
responsibilities
evaluate different silicon solutions for executing mipi and other io peripheries: off-the-shelf components, vendor co-developments and custom designs.
drive vendor execution in various engagements: standard component, build to specification, and co-developments.
collaborate closely with software, design, verification, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
create high performance hardware/software interfaces.
collaborate in developing a new SOC.