דרושים » הנדסה » CAD -Physical Design

A problem isnt truly solved until its solved for all. Thats why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, youll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. Youll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.
As a Technical Program Manager for Silicon engineering, you will use your technical and management experience to justify, plan, coordinate, and deliver custom silicon products. You will plan programs and manage their execution from early concepts through development to tapeout and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life-cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Justify, plan, and coordinate the delivery of custom silicon products, ensuring they meet technical specifications and business objectives.
Drive alignment and collaboration across the internal silicon ecosystem from design and verification to supply chain and quality to ensure seamless execution and operational readiness.
Lead the development of credible schedules and milestones, proactively identifying technical or timeline risks and negotiating trade offs between what is needed and what is possible.
Guide the selection, qualification, and management of external partners serving as the primary technical and program interface.
Negotiate agreements and Statement of Works (SOWs) while managing vendor performance, quality, and costs to protect the supply chain against disruptions and capacity constraints.

We are looking for an experienced ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do:
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities:
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do:
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities:
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

This role is for an analog layout IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.

Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs.
As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following:
Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies.
Reviewing and analyzing floor-plans and complex circuits with circuit designers.
Running complete set of design verification tools available on AMS blocks.
Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed.
Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
Exceeding engineering specifications and expectations by working closely with the circuit design team.
Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance of every detail?
Come join our growing wireless silicon development team!
As part of our Silicon Technologies group, youll help design our next-generation, power-efficient, system-on-chip (SoC). Our wireless SoC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. Joining this group means youll be responsible for crafting and building the technology that fuels our devices. Together, you and your team will enable our customers to do all the things they love with their devices.

If you enjoy a fast-paced and challenging environment, and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.

Responsibility of block and/or sub-system micro-architecture and design implementation.
Work with architects and system teams to define the right solution for the product requirements.
Implement block and/or sub-system design, analyze performance and power and support verification teams.
Responsibility of FE flows such as synthesis, CDC, RDC and Lint to ensure high quality production worthy design.

Our Chip Design team is growing! Join our high-end product design team and help shape the next generation of advanced semiconductor solutions. About us our company  has been delivering tens of millions of chips annually to leading tier-1 customers in the Security, Cloud, and Computing domains. We specialize in semi-custom, high-quality solutions, going above and beyond to meet our customers needs. Our Israel Design Center is fully self-contained, covering everything from product definition and architecture to design, software, validation, and TEST - meaning real ownership and no daily late-night calls across time zones We also pride ourselves on a warm, open culture where everyone knows each other, and every engineer can clearly see the impact of their work on the final silicon. We are looking for experienced Chip Design Engineers to join our team and take a key role in RTL design, new IP development, and SOC integration As part of the design team, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks. Responsibilities
* RTL design and implementation of new IPs
*  SOC integration and design ownership of chip subsystems
* Exploration and evaluation of new protocols and architectural solutions
* Close collaboration with architecture, verification, validation, software, and back-end teams
* Delivering high-quality, best-in-class RTL that meets performance, power, and area goals Why Join Us?
* Work on cutting-edge, high-volume silicon products
* Real impact on end-to-end chip development
* Collaborative environment with strong technical ownership
* A stable yet agile organization with a human, people-first culture

In your role as a senior PHY Algorithms Development Engineer, as part of Apple Connectivity Group, you will be part of a world-class group that pioneers design and development of Physical Layer algorithms for wireless communication systems for Apple products. We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problem in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

We are looking for a candidate who can innovate and integrate signal processing technologies for solving novel and diverse sets of problems in various wireless communication and sensing technologies:
- Develop communication signal processing algorithms for best-in-class implementation of various wireless standards.
- Conduct basic research of existing solutions in literature.
- Involvement in block level spec definition.
- Perform mathematical analyses of the given problem and its proposed solutions.
- Implement floating-point simulations to prove spec compliance of suggested solutions.
- Implement fixed-point modeling and simulation to allow performance sign-off and RTL bit-exact development.
- Write detailed design documents that will enable implementation of algorithms by other teams specializing in either RTL design or DSP firmware coding.
- Optimize and fine-tune the system for spec compliance on silicon in an RF lab environment.

In your role as a senior PHY Algorithms Development Engineer, as part of our Connectivity Group, you will be part of a world-class group that pioneers design and development of Physical Layer algorithms for wireless communication systems for our products. We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. We are meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problem in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

We are looking for a candidate who can innovate and integrate signal processing technologies for solving novel and diverse sets of problems in various wireless communication and sensing technologies:
- Develop communication signal processing algorithms for best-in-class implementation of various wireless standards.
- Conduct basic research of existing solutions in literature.
- Involvement in block level spec definition.
- Perform mathematical analyses of the given problem and its proposed solutions.
- Implement floating-point simulations to prove spec compliance of suggested solutions.
- Implement fixed-point modeling and simulation to allow performance sign-off and RTL bit-exact development .
- Write detailed design documents that will enable implementation of algorithms by other teams specializing in either RTL design or DSP firmware coding .
- Optimize and fine-tune the system for spec compliance on silicon in an RF lab environment.

Required Senior Application Engineer
Description:
Chips talk, We Listen
A game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we depend on computing systems daily. But how can we guarantee their safety, reliability and functionality? we are ithe first-ever company to provide visibility into next-gen chips while they are operating, based on the power of on-chip monitoring, machine learning, and data analytics.
Here, you'll be part of a team that's unlocking deep insights to make electronics more reliable, efficient, and high-quality. We're trusted by industry leaders in data centers, automotive, communications, and consumer devices - we work with the world's largest and most notable companies in tech.
Why this is a great place to work:
Fast-paced and impactful: We're a mission-driven startup, so you'll tackle new challenges daily, wear many hats, and see your work directly influence the future of electronics.
Supportive company culture: Learn from the best. Our 200+ team members are experts in their field with a proven track record of success, and they're committed to fostering a collaborative and supportive work environment.
International presence: We're a multinational company with a diverse team across multiple locations around the globe. You'll collaborate on projects with international impact, gaining a global perspective of the tech industry.
Work with industry leaders: Our solutions are used by the biggest names in tech. You'll be part of the team creating the next generation of groundbreaking products.
Cutting-edge playground: We use the latest machine learning, platforms, and tools to push boundaries and achieve breakthroughs.
Real-world impact: Our work keeps data centers, cars, and other critical systems running smoothly. Your work will directly contribute to safer, more reliable electronics.
We are here for the win: Backed by industry veterans and leading investors, we offer a stable and secure work environment with plenty of room for growth.
We are looking for a Senior Application Engineer to join a global team of Application Engineers that own a technical success and customer satisfaction across multiple high-impact projects.
Responsibilities:
Provide close support to customers and deploy our technology across multiple projects
Provide training to customers on our tools and present our technology
Ability to plan, prioritize tasks/issues and take them to full resolution
Provide continuous feedback to R&D to improve the product.