דרושים » חשמל ואלקטרוניקה » Experienced Verification Team Leader - FPGA/ASIC #1294

we are looking for a Senior CAD Engineer.
What you'll do
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

we are looking for a ASIC Logic Design Engineering Technical Leader.
our Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are now looking for a Senior verification manager for our FC Switch Silicon team. As a FullChip verification manager in NVIDIA's Networking business unit, you'll lead a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
Work in a FC team, responsible to integrate and verify the Switch at system level.
Lead and grow a team of FullChip verification engineers.
Responsible to drive the FullChip verification execution, including staging plan of the projects and deliveries.
Provide technical guidance, mentoring, and support to engineers in the team.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.
Dynamic verification environments planning for units infrastructures and system level.
Work with design/verification team which develops core units within the Switch silicon.

we are a global leader in control systems for quantum computing, a field on the verge of exponential growth. Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers. Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
The hardware development team spans two global sites - one in Tel Aviv and one in Copenhagen. The two teams work seamlessly together across projects, and we try to foster an open dialogue to foster creativity and commitment. The hardware team is responsible for all hardware within our company spanning from room-temperature control hardware to our cryogenic QPU carriers.
We are seeking a Digital Electrical Design Engineer with extensive experience in board-level digital design, high-speed interfaces, and embedded systems. In this role, youll be a technical lighthouse within our Hardware R&D team-guiding complex, high-speed digital designs from concept through production. Youll collaborate closely with firmware engineers, system architects, and other cross-functional teams spread across multiple global sites. While prior quantum or cryogenic experience isnt required, an interest in learning about these cutting-edge fields is a plus.
Key Responsibilities:
Digital Board-Level Design: Architect, design, and implement advanced digital solutions involving FPGAs, microcontrollers, and high-speed communication interfaces (multi-GHz range).
High-Speed Signal Integrity: Develop and validate clocking solutions up to the tens of GHz range and handle GT lines to ensure robust, reliable performance.
End-to-End Development: Own the entire hardware lifecycle-from concept and schematic design in Altium to layout review, testing, and production release.
Design for Manufacturing & Test (DFM/DFT): Integrate manufacturing and testing considerations into your designs, collaborating with supply chain and production teams to ensure scalability and cost-effectiveness.
Technical Collaboration: Work closely with firmware engineers, system architects, and cross-site R&D teams to ensure seamless hardware-firmware integration.
Remote Coordination: Engage in significant remote collaboration with minimal travel, leveraging Agile and Kanban methodologies for project execution.
Subject Matter Expert: Serve as a go-to resource for digital design best practices, helping to maintain high engineering standards across the organization.

We are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, we are the place to develop your skills, innovate, and grow your career.
Why join us?
* Work on cutting-edge automotive projects.
* Learn from a talented and supportive team.
* Gain exposure to real-world automotive challenges.
* Grow your career in a collaborative and inspiring environment.
If youre ready to take the next step in your career and be part of something meaningful, wed love to meet you!
About The Position:
As a Junior ASIC Design Engineer, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where youll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions.
* Support and learn from real emulation platforms used in production-grade designs.
* Contribute to RTL implementation and gain practical experience in design flows.
* Assist with verification and backend (BE) activities, learning industry best practices.
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are looking for a passionate and experienced software developer to join our Chip Design Technologies group, helping to build the tools that shape the future of Chip Design and Verification. This role is at the intersection of software engineering and hardware design. Youll work on the software that accelerates the development of NVIDIAs industry-leading networking chips - highway for the AI revolution.

We're looking for someone who combines strong coding skills with a solid understanding of chip design or verification. If youre excited about solving technical bottlenecks, building scalable tools, and collaborating with designers and verification experts, youll feel right at home here.

What youll be doing:

Develop software tools for our chip design and verification flows

Collaborate closely with designers and verification engineers to identify bottlenecks, propose improvements, and build software solutions that boost productivity and quality.

Own your solutions end-to-end - from idea to delivery to support.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. Additionally, you will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

We are seeking a highly motivated SoC Architect to join our team and define the next generation of our companys high-performance networking SoCs. Our Ethernet and NVL switch silicon powers the world's most advanced AI compute clusters - from hyperscale GPU systems used to train and inference massive foundation models, to the AI factories shaping the future of computing.
As an SoC Architect at our company, you will drive end-to-end SoC definition, connecting system-level requirements with chip-level implementation across multiple domains. You will work closely with cross-functional teams to craft scalable, power-efficient, and feature-rich SoCs that enable the next leap in networking and AI infrastructure.
What You'll Be Doing:
Lead SoC architecture across multiple teams and disciplines - including firmware, security, debug, power management, and peripheral/IP owners - ensuring holistic architectural alignment and system coherence.
Ensure next-generation architectures meet the requirements and constraints of all stakeholder teams, and drive clear specification and communication of those requirements.
Architect and analyze multi-chip solutions, including die-to-die connectivity, chip partitioning, package/board constraints, system requirements, chip fabric, PCIe subsystem and how SoC subsystems must support them.
Define top-level SoC structure: subsystem partitioning, interconnect, memory subsystem, coherency, clocking, power architecture, and system integration.
Define system flows: power up sequences, boot sequences, software update.
Own the SoC architecture specification and guide it throughout the entire product lifecycle - concept, modeling, implementation, and silicon bring-up.
Perform trade-off analyses across performance, area, power, and feature complexity to drive architectural decisions.
Collaborate deeply with chip architects, logic design, verification, physical design, firmware, and system software to ensure seamless integration of all SoC components.
Contribute to innovation and long-term architectural direction, including patent development.